Stress memorization technique for strain coupling enhancement in bulk finFET device

• US 9,431,521 B1
• Filed: 09/18/2015
• Issued: 08/30/2016
• Est. Priority Date: 09/18/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Li, Juntao, Yeh, Chun-Chen
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US14/858,871
• Time in Patent Office: 347 Days
• Field of Search: 438/286, 438/83, 438/285, 438/284, 438/151, 257/401, 257/287, 257/288, 257/E21.703, 257/E27.014
• US Class Current: 1/1
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76205 in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 : the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7847 : using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7849 : the means being provided under the channel
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate

Abstract

A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.

Claims

1. A method for forming strained fins, comprising:

etching trenches in a bulk substrate to form fins;

filling the trenches with a dielectric fill;

recessing the dielectric fill into the trenches to form shallow trench isolation regions;

etching the fins above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins;

forming gate structures over the top portions of the fins;

epitaxially growing raised source ad drain regions on opposite sides of the gate structure; and

performing a pre-amorphization implant to generate defects in the substrate to induce strain and to couple the strain into the top portions of the fins.

2. The method as recited in claim 1, further comprising performing a stress memorization technique (SMT) anneal to propagate the strain after the pre-amorphization implant.

3. The method as recited in claim 1, wherein etching trenches in the bulk substrate to form fins includes:

forming mandrels; and

forming spacers on the mandrels to form an etch mask for etching the trenches.

4. The method as recited in claim 1, wherein filling the trenches with the dielectric fill includes:

depositing a high aspect ratio process (HARP) oxide into the trenches and over the substrate; and

planarizing the HARP oxide to a top of the fins.

5. The method as recited in claim 1, wherein etching the fins above the shallow trench isolation regions includes:

oxidizing the fins above the shallow trench isolation regions; and

wet etching the fins above the shallow trench isolation regions.

6. The method as recited in claim 1, wherein performing the pre-amorphization implant includes implanting ion species into the substrate to cause the defects.

7. The method as recited in claim 6, wherein the ion species include Ge or Xe.

8. The method as recited in claim 1, further comprising protecting a planar region from processing for planar devices.

9. The method as recited in claim 1, wherein recessing the dielectric fill includes recessing the dielectric fill using a SiCoNi etch chemistry.