Super-high density trench MOSFET

• US 9,431,530 B2
• Filed: 05/26/2010
• Issued: 08/30/2016
• Est. Priority Date: 10/20/2009
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Xu, Robert Q., Chen, Kuo-In, Lichtenberger, Karl, Shi, Sharon, Chen, Qufei, Terrill, Kyle
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US12/788,158
• Publication Number:
  US 20110089486A1
• Time in Patent Office: 2,288 Days
• Field of Search: 438279-282, 438/302, 438/268, 257328-330, 257E29277-E29279
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method, in one embodiment, can include forming a plurality of trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET). In addition, the method can include angle implanting source regions into the body region. Furthermore, dielectric material can be grown within the plurality of trenches. Gate polysilicon can be deposited within the plurality of trenches. Moreover, the method can include chemical mechanical polishing the gate polysilicon. The method can also include etching back the gate polysilicon within the plurality of trenches.

Claims

1. A method comprising:

forming a plurality of trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET);

growing dielectric material within said plurality of trenches;

depositing gate polysilicon within said plurality of trenches;

chemical mechanical polishing said gate polysilicon;

etching back said gate polysilicon within said plurality of trenches; and

after said etching back, angle implanting source regions into said body region, a source region contacts both a first trench surface and a second trench surface, said source region is continuous between said first and second trench surfaces.

2. The method of claim 1, further comprising:

depositing dielectric material over said etched back gate polysilicon; and

chemical mechanical polishing said dielectric material.

3. The method of claim 2, further comprising:

self-aligning a source contact over said dielectric material and said source regions.

4. The method of claim 3, wherein said source contact is in contact with at least one of said source regions.

5. The method of claim 1, further comprising:

forming an epitaxial region on a substrate.

6. The method of claim 5, wherein said epitaxial region is P−

and said substrate is P++.

7. The method of claim 5, wherein said epitaxial region is N−

and said substrate is N++.

8. A method comprising:

forming an edge termination trench and a plurality of trenches in an epitaxial region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET);

growing dielectric material within said edge termination trench and within said plurality of trenches;

depositing polysilicon within said edge termination trench and within said plurality of trenches;

chemical mechanical polishing said polysilicon;

etching back said polysilicon within said edge termination trench and within said plurality of trenches; and

after said etching back, angle implanting source regions into a body region of said vertical MOSFET, a source region contacts both a first trench surface and a second trench surface, said source region is continuous between said first and second trench surfaces.

9. The method of claim 8, further comprising:

forming said body region within said epitaxial region, wherein said edge termination trench surrounds said body region.

10. The method of claim 8, further comprising:

forming an epitaxial region on a substrate.

11. The method of claim 8, wherein said source region contacts said dielectric material within a first trench.

12. The method of claim 8, further comprising:

depositing dielectric material over said etched back polysilicon; and

chemical mechanical polishing said dielectric material.

13. The method of claim 12, further comprising:

depositing a low temperature oxide (LTO) and borophosphosilicate glass (BPSG) above said dielectric material.

14. The method of claim 12, further comprising:

self-aligning a source contact over said dielectric material and said source regions.

15. The method of claim 14, wherein said source contact is in contact with at least one of said source regions.