Semiconductor device and method for manufacturing the same

• US 9,431,545 B2
• Filed: 09/06/2012
• Issued: 08/30/2016
• Est. Priority Date: 09/23/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Saito, Toshihiko, Isobe, Atsuo, Hanaoka, Kazuya, Koezuka, Junichi, Sasagawa, Shinya, Kurata, Motomu, Ishizuka, Akihiro
• Primary Examiner(s): Slutsker, Julia
• Assistant Examiner(s): Gondarenko, Natalia
• Application Number:
  US13/604,962
• Publication Number:
  US 20130075732A1
• Time in Patent Office: 1,454 Days
• Field of Search: 257/57, 257/347, 257/E27.112, 257/E21.535, 438/163
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A miniaturized transistor having high electric characteristics is provided with high yield. In a semiconductor device including the transistor, high performance, high reliability, and high productivity are achieved. In a semiconductor device including a transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, source and drain electrode layers are provided in contact with the oxide semiconductor film and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive film and an interlayer insulating film are stacked to cover the oxide semiconductor film, the sidewall insulating layers, and the gate electrode layer, and the interlayer insulating film and the conductive film over the gate electrode layer are removed by a chemical mechanical polishing method, so that the source and drain electrode layers are formed.

Claims

1. A method for manufacturing a semiconductor device comprising steps of:

forming an oxide insulating film;

forming an oxide semiconductor film over the oxide insulating film;

forming a gate insulating film over the oxide semiconductor film;

forming a gate electrode layer and a first insulating film overlapping with the oxide semiconductor film over the gate insulating film;

selectively introducing a dopant into the oxide semiconductor film using the gate electrode layer and the first insulating film as masks;

forming a sidewall insulating layer covering a side surface of the gate electrode layer and a side surface of the first insulating film over the gate insulating film;

forming a conductive film over the oxide semiconductor film, the gate insulating film, the gate electrode layer, the first insulating film, and the sidewall insulating layer;

forming an interlayer insulating film over the conductive film; and

removing the interlayer insulating film and the conductive film by a chemical mechanical polishing method to expose the gate electrode layer and form a source electrode layer and a drain electrode layer, and to form a groove between the interlayer insulating film and the sidewall insulating layer,

forming a second insulating film so that the second insulating film fills the groove and is in contact with the source electrode layer and the drain electrode layer,

wherein a top surface of the source electrode layer and a top surface of the drain electrode layer are lower than a top surface of the sidewall insulating layer and a top surface of the interlayer insulating film,

wherein the top surface of the sidewall insulating layer and the top surface of the interlayer insulating film are aligned with each other,

wherein an outer surface of each of the source electrode layer and the drain electrode layer is stepped,

wherein an inner surface of each of the source electrode layer and the drain electrode layer is in direct contact with the sidewall insulating layer and the oxide semiconductor film, and

wherein the outer surface of each of the source electrode layer and the drain electrode layer is opposite to the inner surface of each of the source electrode layer and the drain electrode layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein planarization treatment is performed on a surface of the oxide insulating film before the oxide semiconductor film is formed.

3. The method for manufacturing a semiconductor device according to claim 1, wherein oxygen is introduced to the oxide insulating film before the sidewall insulating layer is formed.

7. The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film comprises an aluminum oxide film.

4. A method for manufacturing a semiconductor device comprising steps of:

forming an oxide insulating film;

forming an oxide semiconductor film over the oxide insulating film;

forming a gate insulating film over the oxide semiconductor film;

forming a gate electrode layer and a first insulating film overlapping with the oxide semiconductor film over the gate insulating film;

selectively introducing a dopant into the oxide semiconductor film using the gate electrode layer and the first insulating film as masks;

forming a sidewall insulating layer covering a side surface of the gate electrode layer and a side surface of the first insulating film over the gate insulating film;

forming a conductive film over the oxide semiconductor film, the gate insulating film, the gate electrode layer, the first insulating film, and the sidewall insulating layer;

forming an interlayer insulating film over the conductive film; and

removing the interlayer insulating film and the conductive film by a chemical mechanical polishing method to expose the first insulating film over the gate electrode layer and form a source electrode layer and a drain electrode layer, and to form a groove between the interlayer insulating film and the sidewall insulating layer,

forming a second insulating film so that the second insulating film fills the groove and is in contact with the source electrode layer and the drain electrode layer,

wherein a top surface of the source electrode layer and a top surface of the drain electrode layer are lower than a top surface of the first insulating film, a top surface of the sidewall insulating layer, and a top surface of the interlayer insulating film,

wherein the top surface of the first insulating film, the top surface of the sidewall insulating layer, and the top surface of the interlayer insulating film are aligned with each other,

wherein an outer surface of each of the source electrode layer and the drain electrode layer is stepped,

wherein an inner surface of each of the source electrode layer and the drain electrode layer is in direct contact with the sidewall insulating layer and the oxide semiconductor film, and

wherein the outer surface of each of the source electrode layer and the drain electrode layer is opposite to the inner surface of each of the source electrode layer and the drain electrode layer.

5. The method for manufacturing a semiconductor device according to claim 4, wherein planarization treatment is performed on a surface of the oxide insulating film before the oxide semiconductor film is formed.

6. The method for manufacturing a semiconductor device according to claim 4, wherein oxygen is introduced to the oxide insulating film before the sidewall insulating layer is formed.

8. The method for manufacturing a semiconductor device according to claim 4, wherein the second insulating film comprises an aluminum oxide film.