Circuitry useful for clock generation and distribution

• US 9,432,013 B2
• Filed: 08/29/2014
• Issued: 08/30/2016
• Est. Priority Date: 09/12/2013
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Socionext Inc.
• Inventors: Enright, David Timothy, Dedic, Ian Juso
• Primary Examiner(s): Chen, Sibin
• Application Number:
  US14/473,715
• Publication Number:
  US 20150070066A1
• Time in Patent Office: 732 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H01F 2017/0073 with a special conductive pattern, e.g. flat spiral
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H03H 11/22 providing two or more phase shifted output signals, e.g. n-phase output
• CPC Class Codes: H03K 5/1506 with parallel driven output stages; with synchronously driven series connected output stages

Abstract

An integrated circuit comprising an inductor arrangement, the arrangement comprising: four inductors adjacently located in a group and arranged to define two rows and two columns, wherein: the integrated circuit is configured to cause two of those inductors diagonally opposite from one another in the arrangement to produce an electromagnetic field having a first phase, and to cause the other two of those inductors to produce an electromagnetic field having a second phase, the first and second phases being substantially in antiphase.

Claims

1. An integrated circuit comprising:

first and second inductor arrangements; and

buffer circuitry adapted to receive and buffer four clock signals being the four phases of a four-phase clock signal,

wherein;

each said inductor arrangement comprises four inductors adjacently located in a group and arranged to define two rows and two columns;

the integrated circuit is configured, for each said inductor arrangement, to cause two of the four inductors which are diagonally opposite from one another in that arrangement to produce an electromagnetic field having a first phase, and to cause the other two of those four inductors to produce an electromagnetic field having a second phase, the first and second phases being substantially in antiphase; and

the first and second inductor arrangements are connected to the buffer circuitry such that the electromagnetic fields of the first and second inductor arrangements are generated from respective said clock signals whereby the first and second phases of the first inductor arrangement are substantially in quadrature with the first and second phases, respectively, of the second inductor arrangement.

2. The integrated circuit as claimed in claim 1, further comprising one or more layers, wherein each said inductor is formed in only one said layer or across a plurality of said layers.

3. The integrated circuit as claimed in claim 1, wherein:

the inductors each have one or more turns, and are optionally spiral inductors;

or the inductors have the same size and number of turns as one another.

4. The integrated circuit as claimed in claim 3, wherein:

the direction of the turns of the inductors is configured so that the inductors produce respective electromagnetic fields;

or

the inductors are connected to other circuitry of the integrated circuit or to each other so that the inductors produce respective electromagnetic fields.

5. The integrated circuit as claimed in claim 1, wherein the inductors each have a center and a diameter, and wherein a spacing between the centers of the inductors of each said inductor arrangement is Z times the diameter of at least one of the inductors, where 1≦

Z≦

50, and preferably where 1≦

Z≦

10.

6. The integrated circuit as claimed in claim 1, wherein:

each said inductor arrangement comprises sixteen inductors including said four inductors;

the inductors of each said inductor arrangement are arranged to define four rows and four columns;

the inductors are configured so that each of them produces an electromagnetic field having the first phase or the second phase of the inductor arrangement; and

for each said inductor arrangement, diagonally opposite inductors of any adjacent group of four of said sixteen inductors spanning two rows and two columns produce electromagnetic fields having the same said phase as one another.

7. The integrated circuit as claimed in claim 1, wherein said electromagnetic fields are fluctuating or alternating fields.

8. The integrated circuit as claimed in claim 1, wherein the inductors of each said inductor arrangement are connected together to form a single inductor or two separate inductors.

9. The integrated circuit as claimed in claim 1, wherein:

each said inductor arrangement defines associated null lines along which an effective electromagnetic field of each said inductor arrangement has zero or negligible field strength; and

the first and second inductor arrangements are each located such that one of the null lines of the first inductor arrangement is substantially aligned with one of the null lines of the second inductor arrangement.

10. The integrated circuit as claimed in claim 1, wherein:

the first and second inductor arrangements and the buffer circuitry form a first clock distribution unit, said four clock signals being a first set of four clock signals;

the integrated circuit comprises a second said clock distribution unit, adapted to receive and buffer a second set of four clock signals; and

the first and second clock distribution units are connected such that a set of clock signals output by the buffer circuitry of the first clock distribution unit, which are generated by the buffer circuitry of the first clock distribution unit receiving and buffering the first set of four clock signals, are the second set of four clock signals which are received by the buffer circuitry of the second clock distribution unit.

11. The integrated circuit as claimed in claim 10, wherein:

each said inductor arrangement defines associated null lines along which an effective electromagnetic field of each said inductor arrangement has zero or negligible field strength;

the first and second inductor arrangements of the first clock distribution unit are each located such that one of the null lines of the first inductor arrangement of the first clock distribution unit is substantially aligned with one of the null lines of the second inductor arrangement of the first clock distribution unit;

the first inductor arrangements of the first and second clock distribution units are each located such that one of the null lines of the first inductor arrangement of the first clock distribution unit is substantially aligned with one of the null lines of the first inductor arrangement of the second clock distribution unit; and

the second inductor arrangements of the first and second clock distribution units are each located such that one of the null lines of the second inductor arrangement of the first clock distribution unit is substantially aligned with one of the null lines of the second inductor arrangement of the second clock distribution unit.

12. The integrated circuit as claimed in claim 1, comprising analogue-to-digital converter circuitry or digital-to-analogue converter circuitry.

13. An IC chip comprising an integrated circuit as claimed in claim 1.