Reconfigurable filter

• US 9,432,126 B1
• Filed: 06/25/2014
• Issued: 08/30/2016
• Est. Priority Date: 06/25/2014
• Status: Active Grant

• Current Assignee: Rockwell Collins, Inc. (Raytheon Technologies Corporation d/b/a RTX)
• Original Assignee: Rockwell Collins, Inc. (Raytheon Technologies Corporation d/b/a RTX)
• Inventors: Wyse, Russell D., Hageman, Michael L.
• Primary Examiner(s): Payne, David
• Assistant Examiner(s): Kretzer, Casey
• Application Number:
  US14/314,207
• Time in Patent Office: 797 Days
• US Class Current: 1/1
• CPC Class Codes: H04B 10/69 Electrical arrangements in the receiver
• CPC Class Codes: H04B 10/693 Arrangements for optimizing the preamplifier in the receiver

Abstract

A receiver includes an interface for translating an optical signal into two differential electrical signals for a first amplifier. The first amplifier modifies the two differential electrical signals to produce a first signal that is the amplitude of difference between the two differential electrical signals, which contains the information from the optical signal. A variable gain track and hold amplifier (VGTHA) receives the first signal and a clock signal and provides a conditioned analog signal for digital processing. A clock source provides the clock signal, which is aligned with the peak amplitude of the first signal.

Claims

1. A receiver for translating an input signal to a conditioned analog signal for digital processing, the receiver comprising:

a first amplifier receiving the input signal as two differential input signals and modifying the two differential input signals for providing a difference between the two differential input signals as a first signal;

a clock source for providing a clock signal;

a second amplifier receiving the clock signal from the clock source and the first signal from the first amplifier and holding information in the first signal in response to a timing of the clock signal and providing the conditioned analog signal with information from the first signal.

2. The receiver of claim 1, and further comprising an interface for translating the input signal which is a single-ended optical signal into a differential electrical signal.

3. The receiver of claim 2, wherein the interface further comprises two differential photo diodes to produce two differential electrical signals.

4. The receiver of claim 3, wherein the first amplifier is a differential subtractor amplifier that receives and subtracts the two differential electrical signals from each other to determine an amplitude of the difference between the two differential electrical signals.

5. The receiver of claim 4, wherein the first amplifier comprises two differential transistor pairs each to receive one of the two differential electrical signals.

6. The receiver of claim 5, wherein the second amplifier is a variable gain track and hold amplifier, wherein the timing of the clock signal corresponds to the clock signal reaching a peak amplitude, and wherein at the peak amplitude of the clock signal, the second amplifier provides the conditioned analog signal with information from the first signal.

7. The receiver of claim 6, and further comprising a delay circuit for receiving the clock signal and delaying the clock signal to align the peak amplitude of the clock signal with the peak amplitude of the input signal.

8. The receiver of claim 7, wherein the clock source further comprises a photo diode to translate an optical signal to an electrical signal, a filter to receive the electrical signal and produce a sine wave at a fundamental frequency of the optical signal, and wherein the delay circuit is a phase shifter that receives sine wave and aligns the sine wave with the peak amplitude of the input signal and produce the clock signal.

9. The receiver of claim 1, wherein the second amplifier is a variable gain track and hold amplifier (VGTHA), wherein the VGTHA further comprises an input section having two pairs of transistors with each transistor having a base, an emitter, and a collector, wherein the emitter of each transistor in each pair is coupled, the base of each transistor in the two transistor pairs are cross coupled with each other to receive the first signal, and the collector of each transistor in the two transistor pairs are cross coupled with each other to provide an output signal of the input section of the VGTHA.

10. The receiver of claim 9, wherein the VGTHA further comprises clocked buffers combined to the input section to receive the output signal of the input section and combined to the clock source to receive the clock signal and provide the conditioned analog signal.

11. A receiver for translating an input signal to a conditioned analog signal for digital processing, the receiver comprising:

an interface for translating an optical signal into two differential electrical signals;

a first amplifier receiving the two differential electrical signals and subtracting the two differential electrical signals for providing a first signal with an information from the optical signal;

a clock source for providing a clock signal; and

a second amplifier receiving the clock signal from the clock source and the first signal from the first amplifier and holding the information in response to a timing of the clock signal and providing the conditioned analog signal with the information from the optical signal.

12. The receiver of claim 11, wherein the information from the optical signal is in an amplitude of the difference between the two differential electrical signals, and the two differential electrical signals are substantially the same.

13. The receiver of claim 11, wherein the clock source further comprises a photo diode to translate an optical signal to an electrical signal, a filter to receive the electrical signal and produce a sine wave at a fundamental frequency of the optical signal, and a phase shifter that receives sine wave and aligns the sine wave with a peak amplitude of the difference between the two differential electrical signals and produce the clock signal.

14. The receiver of claim 11, wherein the second amplifier is a variable gain track and hold amplifier (VGTHA), wherein the VGTHA further comprises an input section having two pairs of transistors with each transistor having a base, an emitter, and a collector, wherein the emitter of each transistor in each pair is coupled, the base of each transistor in the two transistor pairs are cross coupled with each other to receive the first signal, and the collector of each transistor in the two transistor pairs are cross coupled with each other to provide an output signal of the input section of the VGTHA.

15. The receiver of claim 14, wherein the VGTHA further comprises clocked buffers combined to the input section to receive the output signal of the input section and combined to the clock source to receive the clock signal and provide the conditioned analog signal.

16. The receiver of claim 11, wherein the second amplifier is a variable gain track and hold amplifier, wherein the timing of the clock signal corresponds to the clock signal reaching a peak amplitude, and wherein at the peak amplitude of the clock signal, the second amplifier provides the conditioned analog signal with the information from the optical signal.

17. A receiver for translating an optical signal to a conditioned analog signal for digital processing, the receiver comprising:

an interface for translating the optical signal into two differential electrical signals;

a first amplifier receiving the two differential electrical signals and modifying the two differential electrical signals for providing a difference between the two differential electrical signals as a first signal;

a clock source for providing a clock signal;

a delay circuit for receiving the clock signal and delaying the clock signal to align a peak amplitude of the clock signal with the first signal; and

a second amplifier receiving the clock signal from the clock source and the first signal from the first amplifier and holding information in the first signal in response to a timing of the clock signal and providing the conditioned analog signal with information from the first signal.

18. The receiver of claim 17, wherein the second amplifier is a variable gain track and hold amplifier (VGTHA), wherein the VGTHA further comprises an input section having two pairs of transistors with each transistor having a base, an emitter, and a collector, wherein the emitter of each transistor in each pair is coupled, the base of each transistor in the two transistor pairs are cross coupled with each other to receive the first signal, and the collector of each transistor in the two transistor pairs are cross coupled with each other to provide an output signal of the input section of the VGTHA.

19. The receiver of claim 18, wherein the clock source further comprises a photo diode to translate an optical signal to an electrical signal, a filter to receive the electrical signal and produce a sine wave at a fundamental frequency of the optical signal, and wherein the delay circuit is a phase shifter that receives sine wave and aligns the sine wave with the peak amplitude of the first signal and produce the clock signal.

20. The receiver of claim 19, wherein the first amplifier is a differential subtractor amplifier that receives and subtracts the two differential electrical signals from each other to determine an amplitude of the difference between the two differential electrical signals.