Circuit and method for clock and data recovery

• US 9,432,176 B2
• Filed: 04/14/2015
• Issued: 08/30/2016
• Est. Priority Date: 04/17/2014
• Status: Active Grant

• Current Assignee: Global UniChip Corp., Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Global UniChip Corp., Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Po-Shing, Yeh, Shih-Han, Wang, Ting-Hao
• Primary Examiner(s): Perez, James M
• Application Number:
  US14/686,763
• Publication Number:
  US 20150304097A1
• Time in Patent Office: 504 Days
• Field of Search: 375354-376
• US Class Current: 1/1
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A clock and data recovery circuit includes a sampling module, a phase detect module, a parallel-to-serial converter and a phase adjust module. The sampling module generates a data signal and an edge signal according to input data, a first clock signal and a second clock signal. The phase detect module detects a phase of the data signal and a phase of the edge signal to generate first output recovered data and a first phase adjust signal. The parallel-to-serial converter performs a parallel-to-serial conversion on the first recovered data and the first phase adjust signal, so as to generate second output recovered data and a second phase adjust signal. The phase adjust module generates the first clock signal and the second clock signal, and adjusts the first clock signal and the second clock signal according to the second output recovered data and the second phase adjust signal.

Claims

1. A clock and data recovery circuit, comprising:

a sampling module configured to generate a data signal and an edge signal according to input data, a first clock signal and a second clock signal;

a phase detect module configured to, based on the data signal and the edge signal, perform a serial-to-parallel conversion and detect a phase difference between the data signal and the edge signal to generate at least one error signal, and to generate first output recovered data and a first phase adjust signal according to the at least one error signal;

a parallel-to-serial converter configured to perform a parallel-to-serial conversion on the first recovered data and the first phase adjust signal, so as to generate second output recovered data and a second phase adjust signal; and

a phase adjust module configured to generate the first clock signal and the second clock signal, wherein the phase adjust module adjusts the first clock signal and the second clock signal di to the second output recovered data and the second phase adjust signal.

2. The clock and data recovery circuit of claim 1, further comprising:

a phase locked loop circuit configured to generate and output at least one reference clock signal to the phase adjust module according to an external clock signal, wherein the phase adjust module generates the first clock signal and the second clock signal according to the least one reference clock signal.

3. The clock and data recovery circuit of claim 2, wherein the phase adjust module comprises:

a first phase interpolator configured to generate the first clock signal according to the at least one reference clock signal and the second output recovered data; and

a second phase interpolator configured to generate the second clock signal according to the at least one reference clock signal and the second phase adjust signal.

4. The clock and data recovery circuit of claim 1, wherein the sampling module comprises:

a data sampler configured to sample the input data to generate the data signal according to the first clock signal; and

an edge sampler configured to detect a rising edge and a falling edge of the input data to generate the edge signal according to the second clock signal.

5. The clock and data recovery circuit of claim 1, wherein the phase detect module comprises:

a serial-to-parallel converter configured to perform the serial-to-parallel conversion on the data signal and the edge signal, so as to generate a parallel data signal and a parallel phase signal; and

a phase detector configured to detect a phase of the parallel data signal and a phase of the parallel phase signal to generate the at least one error signal; and

a filter unit configured to generate the first output recovered data and the first phase adjust signal according to the at least one error signal.

6. The clock and data recovery circuit of claim 5, wherein the filter unit is a digital filter.

7. The clock and data recovery circuit of claim 5, wherein the filter unit is a parallel-processing digital filter configured to process the at least one error signal in parallel to generate the first output recovered data and the first phase adjust signal.

8. A clock and data recovery circuit, comprising:

a phase locked loop circuit;

a first phase interpolator which is electrically coupled to the phase locked loop circuit and is configured to generate a first clock signal;

a second phase interpolator which is electrically coupled to the phase locked loop circuit and is configured to generate a second clock signal, wherein the first clock signal and the second clock signal are different in phase by 90 degrees;

a sampling module configured to receive an input data, the first clock signal, and the second clock signal and accordingly generate a data signal and an edge signal;

a serial-to-parallel converter electrically coupled to the sampling module, being configured to generate a parallel data signal and a parallel phase signal based on the data signal and the edge signal;

a phase detector electrically coupled to the serial-to-parallel converter, and is configured to generate at least one error signal based on the parallel data and phase signals, wherein the serial-to-parallel converter operates at a first operating frequency;

a filter unit electrically coupled to the phase detector to filter output signals of the phase detector; and

a parallel-to-serial converter electrically coupled to the first phase interpolator and the second phase interpolator, and being configured to convert filtered signals, which are outputted from the filter unit, to serial signals that are outputted to the first interpolator and the second interpolator,

wherein the first phase interpolator and the second phase interpolator operate at a second operating frequency, and the second operating frequency is higher than the first operating frequency.

9. The clock and data recovery circuit of claim 8, wherein the filter unit comprises a parallel-processing digital filter.

10. A clock and data recovery method, comprising:

respectively sampling input data according to a first clock signal and a second clock signal to generate a data signal and an edge signal;

based on the data signal and the edge signal, performing a serial-to-parallel conversion and then detecting a phase difference between a parallel data signal and a parallel phase signal, in order to generate at least one error signal;

generating first output recovered data and a first phase adjust signal according to the at least one error signal;

performing a parallel-to-serial conversion on the first output recovered data and the first phase adjust signal in order to generate second output recovered data and a second phase adjust signal; and

adjusting the first clock signal and the second clock signal according to the second output recovered data and the second phase adjust signal.

11. The clock and data recovery method of claim 10, further comprising:

transmitting an external clock signal to a phase locked loop circuit to generate at least one reference clock signal;

transmitting the at least one reference clock signal to a first phase interpolator to generate the first clock signal; and

transmitting the at least one reference clock signal to a second phase interpolator to generate the second clock signal.

12. The clock and data recovery method of claim 10, wherein the step of generating the data signal and the edge signal comprises:

sampling the input data according to the first clock signal to generate the data signal; and

detecting a rising edge and a falling edge of the input data according to the second clock signal to generate the edge signal;

wherein the first clock signal and the second clock signal are different in phase by 90 degrees.

13. The clock and data recovery method of claim 10, wherein the step of generating the at least one error signal comprises:

performing the serial-to-parallel conversion on the data signal and the edge signal to generate the parallel data signal and the parallel phase signal; and

detecting a phase of the parallel data signal and a phase of the parallel phase signal to generate the at least one error signal;

transmitting the at least one error signal to a filter unit to generate the first output recovered data and the first phase adjust signal comprises;

transmitting the at least one error signal to a filter unit to generate the first output recovered data and the first phase adjust signal.

14. The clock and data recovery method of claim wherein the filter unit is a parallel-processing filter configured to parallel-process the at least one error signal to generate the first output recovered data and the first phase adjust signal.