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Distributed load balancer node architecture

  • US 9,432,245 B1
  • Filed: 04/16/2013
  • Issued: 08/30/2016
  • Est. Priority Date: 04/16/2013
  • Status: Active Grant
First Claim
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1. A device, comprising;

  • a first network interface controller (NIC) configured to receive packets from and transmit packets onto a first network;

    a second NIC configured to receive packets from and transmit packets onto a second network; and

    a multicore packet processor comprising;

    a first receive core configured to receive packets from the first NIC and, for each received packet, output the packet to one of a plurality of output queues of the first receive core according to a hash function applied to source and destination address information of the packet;

    a second receive core configured to receive packets from the second NIC and, for each received packet, output the packet to one of a plurality of output queues of the second receive core according to a hash function applied to source and destination address information of the packet;

    a first transmit core configured to output processed packets to the first NIC, the first transmit core coupled to a respective plurality of input queues to the first transmit core;

    a second transmit core configured to output processed packets to the second NIC, the second transmit core coupled to a respective plurality of input queues to the second transmit core; and

    a plurality of worker cores each coupled to a respective one of the plurality of output queues of the first receive core and to a respective one of the plurality of output queues of the second receive core, each worker core also coupled to a respective one of the plurality of input queues of the first transmit core and to a respective one of the plurality of input queues of the second transmit core, wherein each worker core is configured to;

    read packets from its respective ones of the output queues of the first receive core and the second receive core;

    for each packet, determine if the packet is to be accepted for processing; and

    for each accepted packet;

    perform one or more processing tasks on the packet;

    determine, according to a protocol of the packet, that either the first transmit core or the second transmit core is to output the packet; and

    output the processed packet to the respective input queue of the determined transmit core.

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