System, method, and computer program product for improving memory systems
First Claim
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1. An apparatus, comprising:
- a first semiconductor platform including a first memory;
a second semiconductor platform including a second memory; and
at least one circuit in electrical communication with at least one of the first semiconductor platform or the second semiconductor platform for transforming a plurality of commands or packets, or a portion thereof, in connection with at least one of the first memory or the second memory, by;
transforming a first memory command or packet, or a portion thereof, such that the first memory command or packet, or the portion thereof, is processed by the first memory of the first semiconductor platform and the first memory command or packet, or the portion thereof, avoids processing, at least in part, by the second memory of the second semiconductor platform; and
transforming a second memory command or packet, or a portion thereof, such that the second memory command or packet, or the portion thereof, avoids processing, at least in part, by the first memory of the first semiconductor platform and the second memory command or packet, or the portion thereof, is processed by the second memory of the second semiconductor platform.
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Accused Products
Abstract
A system, method, and computer program product are provided for a memory system. The system includes a first semiconductor platform including at least one first circuit, and at least one additional semiconductor platform stacked with the first semiconductor platform and including at least one additional circuit.
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Citations
19 Claims
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1. An apparatus, comprising:
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a first semiconductor platform including a first memory; a second semiconductor platform including a second memory; and at least one circuit in electrical communication with at least one of the first semiconductor platform or the second semiconductor platform for transforming a plurality of commands or packets, or a portion thereof, in connection with at least one of the first memory or the second memory, by; transforming a first memory command or packet, or a portion thereof, such that the first memory command or packet, or the portion thereof, is processed by the first memory of the first semiconductor platform and the first memory command or packet, or the portion thereof, avoids processing, at least in part, by the second memory of the second semiconductor platform; and transforming a second memory command or packet, or a portion thereof, such that the second memory command or packet, or the portion thereof, avoids processing, at least in part, by the first memory of the first semiconductor platform and the second memory command or packet, or the portion thereof, is processed by the second memory of the second semiconductor platform. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method, comprising:
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transforming a first memory command or packet, or a portion thereof, such that the first memory command or packet, or the portion thereof, is processed by a first memory of a first semiconductor platform and the first memory command or packet, or the portion thereof, avoids processing, at least in part, by a second memory of a second semiconductor platform; and transforming a second memory command or packet, or a portion thereof, such that the second memory command or packet, or the portion thereof, avoids processing, at least in part, by the first memory of the first semiconductor platform and the second memory command or packet, or the portion thereof, is processed by the second memory of the second semiconductor platform. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A computer program product embodied on a non-transitory computer readable medium, comprising:
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code for working with at least one circuit to transform a first memory command or packet, or a portion thereof, such that the first memory command or packet, or the portion thereof, is processed by a first memory of a first semiconductor platform and the first memory command or packet, or the portion thereof, avoids processing, at least in part, by a second memory of a second semiconductor platform; and code for working with the at least one circuit to transform a second memory command or packet, or a portion thereof, such that the second memory command or packet, or the portion thereof, avoids processing, at least in part, by the first memory of the first semiconductor platform and the second memory command or packet, or the portion thereof, is processed by the second memory of the second semiconductor platform. - View Dependent Claims (14, 15, 16, 17, 18)
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19. An apparatus, comprising:
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a first semiconductor platform including a first memory; a second semiconductor platform including a second memory; means for transforming a first memory command or packet, or a portion thereof, such that the first memory command or packet, or the portion thereof, is processed by the first memory of the first semiconductor platform and the first memory command or packet, or the portion thereof, avoids processing, at least in part, by the second memory of the second semiconductor platform; and means for transforming a second memory command or packet, or a portion thereof, such that the second memory command or packet, or the portion thereof, avoids processing, at least in part, by the first memory of the first semiconductor platform and the second memory command or packet, or the portion thereof, is processed by the second memory of the second semiconductor platform.
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Specification