Testing of thru-silicon vias

• US 9,435,846 B2
• Filed: 05/20/2014
• Issued: 09/06/2016
• Est. Priority Date: 05/21/2013
• Status: Active Grant

• Current Assignee: Tessera Advanced Technologies Inc (Adeia Inc.)
• Original Assignee: eSilicon Corporation (Inphi Corporation)
• Inventors: DeLaCruz, Javier
• Primary Examiner(s): Koval, Melissa
• Assistant Examiner(s): Maini, Rahul
• Application Number:
  US14/283,116
• Publication Number:
  US 20140347089A1
• Time in Patent Office: 840 Days
• Field of Search: 324755-763
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2601 Apparatus or methods therefor G01R31/2607, G01R31/2642 take precedence
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/52 Testing for short-circuits, leakage current or ground faults

Abstract

A system and a method for testing thru silicon vias (TSVs) in a silicon die. A silicon die containing multiple TSVs is mounted on a wafer tape. Two probe points are probed on the exposed side of the silicon die. A resistance is measured between the two probe points and an electrical integrity is determined based on the measured resistance.

Claims

1. A method for testing thru-silicon vias (TSVs) in a silicon die, the TSVs for providing interconnection between opposite sides of the silicon die, the method comprising:

mounting the silicon die on wafer tape, the wafer tape having a resistivity that is sufficiently low to form a conductive path between TSVs;

for different sets of two probe points, contacting the two probe points on the exposed side of the silicon die, each probe point electrically connected to one of two different TSVs, wherein the different sets of two probe points are a same pair of probe points on different dies;

measuring a resistance between the two probe points; and

determining an electrical integrity of the two TSVs based on the measured resistance.

2. The method of claim 1, wherein the silicon die comprises contacts with a first pitch on the exposed side of the silicon die and contacts with a second pitch on the taped side of the silicon die, and the first pitch is less than the second pitch.

3. The method of claim 1, wherein the silicon die comprises contacts with a first pitch on the exposed side of the silicon die and contacts with a second pitch on the taped side of the silicon die, and the first pitch is larger than the second pitch.

4. The method of claim 1, wherein determining the electrical integrity of the two TSVs comprises:

determining a presence of a defect, based on the measured resistance relative to a threshold resistance.

5. The method of claim 4, wherein the defect is a short and determining the electrical integrity of the two TSVs comprises determining that a short exists if the measured resistance is below the threshold resistance.

6. The method of claim 4, wherein the defect is an open and determining the electrical integrity of the two TSVs comprises determining that an open exists if the measured resistance is above the threshold resistance.

7. The method of claim 4, wherein the threshold resistance is a predetermined threshold resistance.

8. The method of claim 4, further comprising:

determining a statistical distribution of the measured resistances between the two probe points; and

determining the threshold resistance based on a statistical distribution of the measured resistances.

9. The method of claim 8, wherein determining the electrical integrity of the two TSVs comprises:

determining a presence of a defect, if the measured resistance is an outlier of the statistical distribution of the measured resistances.

10. The method of claim 8, wherein the defect is a short and determining the electrical integrity of the two TSVs comprises determining that a short exists if the measured resistance is a threshold amount below an average measured resistance.

11. The method of claim 8, wherein the defect is an open and determining the electrical integrity of the two TSVs comprises determining that an open exists if the measured resistance is a threshold amount above an average measured resistance.

12. The method of claim 8, wherein the threshold resistance is based on an average and on a standard deviation of the statistical distribution.

13. The method of claim 4, further comprising:

for different sets of two probe points, contacting the two probe points and measuring resistances between the two probe points; and

determining a presence of a defect in an individual TSV based on two or more measured resistances in which one probe point is connected to that individual TSV and the other probe point is connected to a different TSV.

14. The method of claim 1, wherein the wafer tape comprises a photo sensitive adhesive.

15. The method of claim 1, wherein the wafer tape is mounted on a wafer ring, the wafer ring comprising at least one alignment mark.

16. The method of claim 1, wherein a resistivity of the wafer tape is higher than a resistivity of the TSVs.

17. A non-transitory computer readable medium storing instructions for testing thru-silicon vias (TSVs) in a silicon die, the TSVs for providing interconnection between opposite sides of the silicon die, the instructions when executed by a processor cause the processor to:

receive a resistance measurement between different sets of two probe points of the silicon die, the silicon die mounted on a wafer tape, the wafer tape having a resistivity that is sufficiently low to form a conductive path between TSVs, each probe point electrically connected to one of two different TSVs, wherein the different sets of two probe points are a same pair of probe points on different dies; and

determine an electrical integrity of the two TSVs based on the received resistance measurement.

18. The non-transitory computer readable medium of claim 17, wherein determining an electrical integrity of the two TSVs comprises determining a presence of a defect, wherein the defect is one of:

a short and determining the electrical integrity of the two TSVs comprises determining that a short exists if the measured resistance is below a first threshold resistance; and

an open and determining the electrical integrity of the two TSVs comprises determining that an open exists if the measured resistance is above a second threshold resistance;

wherein the first threshold resistance and the second threshold resistance are based on a resistance of a TSV and the resistivity of the wafer tape.