Flat display panel having narrow bezel

• US 9,436,049 B2
• Filed: 11/15/2013
• Issued: 09/06/2016
• Est. Priority Date: 11/30/2012
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Heo, Seungho, So, Byeongseong
• Primary Examiner(s): Nguyen, Sang V
• Application Number:
  US14/082,022
• Publication Number:
  US 20140152935A1
• Time in Patent Office: 1,026 Days
• Field of Search: 349/40, 349/138, 349/139
• US Class Current: 1/1
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2202/16 conductive

Abstract

The present disclosure relates to reducing bezel area of a flat display panel comprising a substrate with a non-display area surrounding a display area, the display area comprising common lines coupled to corresponding rows of pixels; and a gate driver formed in the non-display area. The display may further include a conductive sealing region formed in the non-display area and configured to supply a common line voltage; and a plurality of common pads formed within the conductive sealing region and each coupled to a corresponding one of the common lines to apply a common line voltage to the rows of pixels. Alternatively, the display may further include a vertical common line formed in the non-display area between the gate driver and the display area, the vertical common line extending from top to bottom of the non-display area and coupled to said common lines to apply a common voltage.

Claims

1. A flat display panel, comprising:

a substrate including a display area and a non-display area surrounding the display area, the display area comprising a plurality of common lines each coupled to a corresponding one of a plurality of rows of pixels;

a gate in panel (GIP) gate driver formed in the non-display area of the substrate;

a conductive sealing region formed in the non-display area, the conductive sealing region surrounding the gate driver, the conductive sealing region including conductive sealant supplying a common line voltage throughout an entirety of the conductive sealing region; and

a plurality of common pads formed within the conductive sealing region and each coupled to a corresponding one of the common lines to apply the common line voltage to said corresponding one of the rows of pixels, the common line voltage supplied to the plurality of common pads through the conductive sealant surrounding each common pad, the conductive sealant electrically connecting the plurality of common pads directly to each other,

wherein the plurality of common pads are disposed proximate to a first side of the gate driver, and the display area is disposed proximate to a second side of the gate driver opposite the first side.

2. The flat display panel according to claim 1, wherein the display area comprises a plurality of gate lines each coupled to said corresponding one of the rows of pixels, and wherein the gate driver formed in the non-display area between the display area and the conductive sealing region is configured to apply gate signals to the gate lines.

3. The flat display panel according to claim 1, wherein said gate lines are substantially parallel to said common lines within the display area.

4. The flat display panel according to claim 1, wherein the common pads and conductive sealant disposed in the conductive sealing region directly contact each other to make an electric connection.

5. The flat display panel according to claim 1, wherein the common pads are electrically connected to common pad terminals via contact holes formed in an insulating layer disposed to cover the common pads, the conductive sealant in contact with the common pad terminals to provide the direct electrical connection among the common pad terminals to each other.

6. The flat display panel according to claim 1, wherein the conductive sealant receives the common line voltage from a data driver disposed on an upper edge of the display panel, the conductive sealant electrically connecting the data driver to the plurality of common pads.

7. The flat display panel according to claim 1, wherein the gate driver comprises a plurality of gate driving circuits connected to a plurality of gate lines, and the plurality of gate lines each correspond to at least one of the common lines corresponding to one of the rows of pixels.

8. The flat display panel according to claim 1, wherein a width of the bezel is between 6.5 mm and 10 mm.

9. The flat display panel according to claim 8, wherein a width of the gate driver is between 4.5 mm and 6 mm and a width of the conductive sealing region is 2 mm.

19. The flat display panel according to claim 1, wherein the conductive sealant electrically connects the plurality of common pads directly to each other without any common line electrically connecting the plurality of common pads to each other within the conductive sealing region.

10. A flat display panel, comprising:

a substrate including a display area and a non-display area surrounding the display area, the display area comprising a plurality of common lines each coupled to a corresponding one of a plurality of rows of pixels;

a gate in panel (GIP) gate driver formed in the non-display area of the substrate;

a conductive sealing region formed in the non-display area, the conductive sealing region surrounding the gate driver, the conductive sealing region including conductive sealant supplying a common line voltage throughout an entirety of the conductive sealing region; and

a plurality of common pads formed within the conductive sealing region and each coupled to a corresponding one of the common lines to apply the common line voltage to said corresponding one of the rows of pixels, the common line voltage supplied to the conductive sealant surrounding each common pad to electrically connect the plurality of common pads directly to each other through the conductive sealant,

wherein a minimum width of the bezel corresponds to a minimum width of the gate driver added to a minimum width of the conductive sealing region formed within the non-display area, the minimum width of the bezel measured between an edge of the flat display panel and an edge separating the display area from the non-display area, and

wherein the plurality of common pads are disposed proximate to a first side of the gate driver, and the display area is disposed proximate to a second side of the gate driver opposite the first side.

11. The flat display panel according to claim 10, wherein the display area comprises a plurality of gate lines each coupled to said corresponding one of the rows of pixels, and wherein the gate driver formed in the non-display area between the display area and the conductive sealing region is configured to apply gate signals to the gate lines.

12. The flat display panel according to claim 10, wherein said gate lines are substantially parallel to said common lines within the display area.

13. The flat display panel according to claim 10, wherein the common pads and conductive sealant disposed in the conductive sealing region directly contact each other to make an electric connection.

14. The flat display panel according to claim 10, wherein the common pads are electrically connected to common pad terminals via contact holes formed in an insulating layer disposed to cover the common pads, the conductive sealant in contact with the common pad terminals to provide the direct electrical connection among the common pad terminals to each other.

15. The flat display panel according to claim 10, wherein the conductive sealant receives the common line voltage from a data driver disposed on an upper edge of the display panel, the conductive sealant electrically connecting the data driver to the plurality of common pads.

16. The flat display panel according to claim 10, wherein the gate driver comprises a plurality of gate driving circuits connected to a plurality of gate lines, and the plurality of gate lines each correspond to at least one of the common lines corresponding to one of the rows of pixels.

17. The flat display panel according to claim 10, wherein a width of the bezel is between 6.5 mm and 10 mm.

18. The flat display panel according to claim 17, wherein a width of the gate driver is between 4.5 mm and 6 mm and a width of the conductive sealing region is 2 mm.

20. The flat display panel according to claim 10, wherein the conductive sealant electrically connects the plurality of common pads directly to each other without any common line electrically connecting the plurality of common pads to each other within the conductive sealing region.