Saving power when in or transitioning to a static mode of a processor
First Claim
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1. A method comprising:
- transitioning a processor to a reduced operation mode within a variable time allowed that varies based on a processor configuration; and
reducing a voltage to the processor by a value dependent on the variable time allowed, wherein the voltage reduced by the value varies with a variation in the voltage and is sufficient to retain a memory state of the processor while the processor operates in the reduced operation mode.
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Abstract
A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.
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Citations
21 Claims
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1. A method comprising:
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transitioning a processor to a reduced operation mode within a variable time allowed that varies based on a processor configuration; and reducing a voltage to the processor by a value dependent on the variable time allowed, wherein the voltage reduced by the value varies with a variation in the voltage and is sufficient to retain a memory state of the processor while the processor operates in the reduced operation mode. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus comprising:
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a processor configured to operate in a reduced operation mode; and a circuit configured to reduce a voltage to the processor by a value dependent on a variable time allowed for the processor to transition to the reduced operation mode, wherein the voltage reduced by the value varies with a variation in the voltage and is sufficient to retain a memory state of the processor while the processor operates in the reduced operation mode, and wherein the variable time allowed varies based on a processor configuration. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A circuit comprising:
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an input terminal; an output terminal; and a voltage regulator coupled to the input and output terminals, wherein the voltage regulator is configured to reduce a voltage to a processor by a value dependent on a variable time allowed for the processor to transition to a reduced operation mode, wherein the voltage reduced by the value varies with a variation in the voltage and is sufficient to retain a memory state of the processor while the processor operates in the reduced operation mode, and wherein the variable time allowed varies based on a processor configuration. - View Dependent Claims (17, 18, 19, 20, 21)
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Specification