Non-intrusive monitoring and control of integrated circuits

• US 9,436,565 B2
• Filed: 05/19/2014
• Issued: 09/06/2016
• Est. Priority Date: 07/04/2013
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Olgiati, Andrea, Baker, Matthew Pond, Teig, Steven
• Primary Examiner(s): Crawford, Jason M
• Application Number:
  US14/281,219
• Publication Number:
  US 20150012782A1
• Time in Patent Office: 841 Days
• Field of Search: 326 37- 41, 326/47, 716/100, 716/136
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/3185 Reconfiguring for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/2205 using arrangements specific to the hardware being tested
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
• CPC Class Codes: G06F 11/3003 Monitoring arrangements specially adapted to the computing system or computing system component being monitored
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An application-specific integrated circuit (ASIC) is provided. The ASIC includes a group of non-configurable circuits customized for performing operations for a particular use. The ASIC also includes a set of reconfigurable circuits for configurably performing a set of operations based on configuration data. The ASIC also includes a configuration and monitoring network that receives a set of signals from the non-configurable circuits of the ASIC. The configuration and monitoring network also receives incremental sets of configuration data while the ASIC is performing operations of the user design. Each incremental set of data is used for reconfiguring the configuration and monitoring network (i) to monitor one or more signals in the set of signals and (ii) to take a set of actions when values of the monitored signals satisfy a condition.

Claims

1. A method of monitoring operations of an integrated circuit (IC), the IC comprising a set of configurable circuits for configurably performing a set of operations based on configuration data, the method comprising:

loading a first set of configuration data into the IC to configure a plurality of configurable circuits in the set of configurable circuits to perform operations of a user design;

receiving a definition of (i) an event based on values of a set of signals in the user design and (ii) a set of corresponding actions to take when the event occurs;

generating an incremental second set of configuration data based on the definition of the event and the set of corresponding actions; and

while the IC is performing the operations of the user design, loading the incremental second set of configuration data into the IC to monitor for the event and to take the set of actions when the event occurs.

2. The method of claim 1, wherein loading the incremental second set of configuration data into the IC does not alter the functionality performed by the parts of the IC under the control the first set of configuration data.

3. The method of claim 1, wherein the first set of configuration data is generated from the user design, wherein generating the incremental second set of configuration data does not require modifying the user design.

4. The method of claim 1, wherein the first set of configuration data is generated by compiling the user design specified in register-transfer language (RTL), wherein generating the incremental second set of configuration data does not require recompiling the user design.

5. The method of claim 1, wherein the set of actions comprises storing a value of one or more signals in the IC.

6. The method of claim 1, wherein the set of actions comprises sending a value of one or more signals to an output port of the IC.

7. The method of claim 1, wherein the set of actions comprises generating a signal to halt the operations of the IC.

8. The method of claim 1, wherein the set of actions comprises reconfiguring a set of configurable circuits in the IC.

9. The method of claim 1, wherein generating an incremental second set of configuration data comprises:

identifying at least one signal in the set of signals used to define the even that is not generated during the operation of the IC; and

reconstructing said at least one signal from a set of signals generated during the operation of the IC.

10. A non-transitory machine readable medium storing a program for monitoring operations of an integrated circuit (IC), the IC comprising a set of configurable circuits for configurably performing a set of operations based on configuration data, the program comprising sets of instructions for:

loading a first set of configuration data into the IC to configure a plurality of configurable circuits in the set of configurable circuits to perform operations of a user design;

receiving a definition of (i) an event based on values of a set of signals in the user design and (ii) a set of corresponding actions to take when the event occurs;

generating an incremental second set of configuration data based on the definition of the event and the set of corresponding actions; and

loading, while the IC is performing the operations of the user design, the incremental second set of configuration data into the IC to monitor for the event and to take the set of actions when the event occurs.

11. The non-transitory machine readable medium of claim 10, wherein loading the incremental second set of configuration data into the IC does not alter the functionality performed by the parts of the IC under the control the first set of configuration data.

12. The non-transitory machine readable medium of claim 10, wherein the first set of configuration data is generated from the user design, wherein generating the incremental second set of configuration data does not require modifying the user design.

13. The non-transitory machine readable medium of claim 10, wherein the first set of configuration data is generated by compiling the user design specified in register-transfer language (RTL), wherein generating the incremental second set of configuration data does not require recompiling the user design.

14. The non-transitory machine readable medium of claim 10, wherein the set of actions comprises storing a value of one or more signals in the IC.

15. The non-transitory machine readable medium of claim 10, wherein the set of actions comprises sending a value of one or more signals to an output port of the IC.

16. The non-transitory machine readable medium of claim 10, wherein the set of actions comprises generating a signal to halt the operations of the IC.

17. The non-transitory machine readable medium of claim 10, wherein the set of actions comprises reconfiguring a set of configurable circuits in the IC.

18. The non-transitory machine readable medium of claim 10, wherein the set of instructions for generating an incremental second set of configuration data comprises a set of instructions for:

identifying at least one signal in the set of signals used to define the even that is not generated during the operation of the IC; and

reconstructing said at least one signal from a set of signals generated during the operation of the IC.