Optimizing placement of circuit resources using a globally accessible placement memory
First Claim
1. A method, executed by one or more processors, for optimizing placement of a logic network, the method comprising:
- partitioning a logic network comprising a plurality of logic elements into a plurality of logic partitions;
launching a plurality of placement optimization threads that correspond to the plurality of logic partitions;
allocating memory that is accessible to the plurality of placement optimization threads to provide a globally accessible placement memory;
reserving a placement location for at least a portion of the plurality of logic elements via the globally accessible placement memory; and
wherein each placement optimization thread of the plurality of placement optimization threads is configured to conduct the operations of;
determining a desired location for a logic element of the plurality of logic elements,reserving, via the globally accessible placement memory, a plurality of potential locations for the logic element that are proximate to the desired location,determining a best location from the plurality of potential locations, andplacing the logic element at the best location.
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Accused Products
Abstract
A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.
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Citations
20 Claims
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1. A method, executed by one or more processors, for optimizing placement of a logic network, the method comprising:
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partitioning a logic network comprising a plurality of logic elements into a plurality of logic partitions; launching a plurality of placement optimization threads that correspond to the plurality of logic partitions; allocating memory that is accessible to the plurality of placement optimization threads to provide a globally accessible placement memory; reserving a placement location for at least a portion of the plurality of logic elements via the globally accessible placement memory; and wherein each placement optimization thread of the plurality of placement optimization threads is configured to conduct the operations of; determining a desired location for a logic element of the plurality of logic elements, reserving, via the globally accessible placement memory, a plurality of potential locations for the logic element that are proximate to the desired location, determining a best location from the plurality of potential locations, and placing the logic element at the best location. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A computer program product for optimizing placement of a logic network, the computer program product comprising:
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one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the program instructions comprising instructions to; partition a logic network comprising a plurality of logic elements into a plurality of logic partitions; launch a plurality of placement optimization threads that correspond to the plurality of logic partitions; allocate memory that is accessible to the plurality of placement optimization threads to provide a globally accessible placement memory; reserve a placement location for at least a portion of the plurality of logic elements via the globally accessible placement memory; and wherein the program instructions comprise instructions for each placement optimization thread of the plurality of placement optimization threads to conduct the operations of; determining a desired location for a logic element of the plurality of logic elements, reserving, via the globally accessible placement memory, a plurality of potential locations for the logic element that are proximate to the desired location, determining a best location from the plurality of potential locations, and placing the logic element at the best location. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A computer system for optimizing placement of a logic network, the computer system comprising:
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one or more computers; one or more computer readable storage media and program instructions stored on the one or more computer readable storage media for execution by at least one of the computers, the program instructions comprising instructions to; partition a logic network comprising a plurality of logic elements into a plurality of logic partitions; launch a plurality of placement optimization threads that correspond to the plurality of logic partitions; allocate memory that is accessible to the plurality of placement optimization threads to provide a globally accessible placement memory; reserve a placement location for at least a portion of the plurality of logic elements via the globally accessible placement memory; and wherein the program instructions comprise instructions for each placement optimization thread of the plurality of placement optimization threads to conduct the operations of; determining a desired location for a logic element of the plurality of logic elements, reserving, via the globally accessible placement memory, a plurality of potential locations for the logic element that are proximate to the desired location, determining a best location from the plurality of potential locations, releasing each of the plurality of potential locations that are not the best location, and placing the logic element at the best location. - View Dependent Claims (17, 18, 19, 20)
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Specification