Secure erase in a memory device

• US 9,436,831 B2
• Filed: 12/19/2013
• Issued: 09/06/2016
• Est. Priority Date: 10/30/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Ellis, Robert W., Lucas, Gregg S.
• Primary Examiner(s): RAHIM, MONJUR
• Application Number:
  US14/135,245
• Publication Number:
  US 20150121537A1
• Time in Patent Office: 992 Days
• Field of Search: 726/26
• US Class Current: 1/1
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 21/60 Protecting data
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2221/2143 Clearing memory, e.g. to prevent the data from being stolen

Abstract

The various implementations described herein include systems, methods and/or devices used to enable secure erase in a memory device. In one aspect, the method includes detecting a secure erase trigger. The method further includes determining a secure erase algorithm from among one or more secure erase algorithms to use in accordance with the detected secure erase trigger. The method further includes performing a secure erase operation in accordance with the selected secure erase algorithm, the secure erase operation including: (1) signaling a secure erase condition to a plurality of controllers on the memory device, (2) erasing one or more non-volatile memory devices on the memory device, (3) monitoring the secure erase operation, and (4) recording data related to the secure erase operation.

Claims

1. A method of erasing data in a memory device, the method comprising:

in the memory device, the memory device having a plurality of hardware controllers;

detecting a secure erase trigger;

determining a secure erase algorithm from among a plurality of secure erase algorithms to use in accordance with the detected secure erase trigger;

performing a secure erase operation in accordance with the determined secure erase algorithm, the secure erase operation including;

signaling a secure erase condition to the plurality of hardware controllers on the memory device;

erasing, in parallel, two or more non-volatile memory devices on the memory device;

monitoring the secure erase operation, wherein monitoring the secure erase operation includes monitoring a completion status of the secure erase operation; and

based on the monitoring, recording data related to the secure erase operation, the recorded data including data indicating the completion status of the secure erase operation.

2. The method of claim 1, further comprising saving data indicating a state of the secure erase operation in response to a loss of power prior to completion of the secure erase operation.

3. The method of claim 1, wherein the plurality of secure erase algorithms include at least one algorithm to overwrite a storage medium with specific overwrite patterns and at least one algorithm other than an overwrite algorithm.

4. The method of claim 1, wherein the secure erase trigger includes a secure erase signal from a host system, and wherein the secure erase signal is communicated from the host system to the memory device through a Serial Presence Detect (SPD) interface.

5. The method of claim 1, wherein at least one of the plurality of secure erase algorithms applies a high energy impulse to destroy the one or more volatile memory devices on the memory device.

6. The method of claim 1, wherein the secure erase trigger is internally generated in the memory device when predefined criteria are satisfied, the predefined criteria including connection of the memory device to a new slot location.

7. The method of claim 1, wherein the secure erase trigger is internally generated in the memory device when predefined criteria are satisfied, the predefined criteria including failure to receive a command to preserve the memory device in a predetermined time period.

8. The method of claim 1, wherein the secure erase trigger is generated by a debug port associated with the memory device, wherein the debug port is password protected.

9. The method of claim 1, wherein the plurality of controllers on the memory device include a storage controller and one or more flash controllers, the one or more flash controllers coupled by the storage controller to a host interface of the memory device.

10. The method of claim 1, wherein the plurality of controllers on the memory device include at least one non-volatile storage controller and at least one other storage controller other than the at least one non-volatile storage controller.

11. The method of claim 1, wherein one of the plurality of controllers on the memory device maps double data rate (DDR) interface commands to serial advance technology attachment (SATA) interface commands.

12. The method of claim 1, wherein erasing one or more non-volatile memory devices on the memory device includes putting the memory device into a state that will erase the one or more non-volatile memory devices on the memory device the next time the memory device is powered up.

13. The method of claim 1, wherein performing a secure erase operation further includes preventing continued operation of the memory device by a host system.

14. The method of claim 1, wherein signaling the secure erase condition to the plurality of controllers on the memory device includes separately signaling the secure erase condition to each of the plurality of controllers.

15. The method of claim 1, wherein erasing one or more non-volatile memory devices on the memory device includes erasing a subset of flash memory devices associated with a flash controller of the plurality of controllers on the memory device.

16. The method of claim 1, wherein erasing one or more non-volatile memory devices on the memory device includes erasing all flash memory devices associated with a flash controller of the plurality of controllers on the memory device.

17. The method of claim 1, wherein erasing one or more non-volatile memory devices on the memory device includes erasing all flash memory devices associated with a subset of flash controllers of the plurality of controllers on the memory device.

18. The method of claim 1, wherein erasing one or more non-volatile memory devices on the memory device includes erasing all flash memory devices associated with all flash controllers of the plurality of controllers on the memory device.

19. The method of claim 1, wherein erasing one or more non-volatile memory devices on the memory device includes erasing the one or more non-volatile memory devices in a predefined sequence.

20. The method of claim 19, wherein the predefined sequence is programmable.

21. The method of claim 1, further comprising blocking host data from being preserved in response to data hardening events that occur while performing the secure erase operation.

22. The method of claim 1, further comprising:

prior to performing the secure erase operation, determining whether a variable is set to prevent the secure erase operation; and

in accordance with a determination that the variable is set, preventing performance of the secure erase operation.

23. The method of claim 1, wherein signaling the secure erase condition to the plurality of hardware controllers on the memory device further comprises:

signaling a first hardware controller of the plurality of hardware controllers to securely erase a first portion of the one or more non-volatile memory devices, and

signaling a second hardware controller of the plurality of hardware controllers to securely erase a second portion of the one or more non-volatile memory devices in parallel with the first hardware controller securely erasing the first portion of the one or more non-volatile memory devices.

24. The method of claim 1, wherein the non-volatile memory comprises one or more flash memory devices.

25. The method of claim 1, wherein the memory device includes a dual in-line memory module (DIMM) device.

26. A memory device, comprising:

an interface for coupling the memory device to a host system;

two or more controllers; and

secure erase circuitry including one or more processors, the secure erase circuitry configured to;

detect a secure erase trigger;

determine a secure erase algorithm from among a plurality of secure erase algorithms to use in accordance with the detected secure erase trigger;

perform a secure erase operation in accordance with the determined secure erase algorithm, the secure erase operation including;

signaling a secure erase condition to a plurality of the two or more controllers on the memory device;

erasing, in parallel, two or more non-volatile memory devices on the memory device;

monitoring the secure erase operation, wherein monitoring the secure erase operation includes monitoring a completion status of the secure erase operation; and

based on the monitoring, recording data related to the secure erase operation, the recorded data including data indicating the completion status of the secure erase operation.

27. The memory device of claim 26, wherein the plurality of controllers on the memory device include a storage controller and one or more flash controllers, the one or more flash controllers coupled by the storage controller to a host interface of the memory device.

28. The memory device of claim 26, wherein the interface for coupling the memory device to a host system comprises a double data rate (DDR) interface, and the secure erase signal from the host system is communicated to the memory device through the double data rate (DDR) interface.

29. The memory device of claim 26, wherein the plurality of secure erase algorithms include at least one algorithm to overwrite a storage medium with specific overwrite patterns and at least one algorithm other than an overwrite algorithm.

30. A non-transitory computer readable storage medium, storing one or more programs for execution by one or more hardware processors of a memory device having a plurality of hardware controllers and secure erase circuitry, the one or more programs including instructions for:

detecting a secure erase trigger;

determining a secure erase algorithm from among a plurality of secure erase algorithms to use in accordance with the detected secure erase trigger;

performing a secure erase operation in accordance with the determined secure erase algorithm, the secure erase operation including;

signaling a secure erase condition to the plurality of hardware controllers on the memory device;

erasing, in parallel, two or more non-volatile memory devices on the memory device;

monitoring the secure erase operation, wherein monitoring the secure erase operation includes monitoring a completion status of the secure erase operation; and

based on the monitoring, recording data related to the secure erase operation, the recorded data including data indicating the completion status of the secure erase operation.