Distributed cascode current source for RRAM set current limitation

• US 9,437,291 B2
• Filed: 01/26/2015
• Issued: 09/06/2016
• Est. Priority Date: 02/26/2014
• Status: Active Grant

• Current Assignee: Hefei Reliance Memory Limited
• Original Assignee: Rambus Inc.
• Inventors: Bateman, Bruce Lynn
• Primary Examiner(s): Hoang, Huan
• Assistant Examiner(s): Dinh, Minh
• Application Number:
  US14/605,866
• Publication Number:
  US 20150243354A1
• Time in Patent Office: 589 Days
• Field of Search: 365/148
• US Class Current: 1/1
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring

Abstract

In one example, a current limited device is coupled between a source line of a memory cell array and a supply voltage, and configured to operate in a constant current mode during an access operation of a memory cell. An array control circuitry may be coupled to the memory cell array, and configured to control the constant current mode and supply an associated select bias voltage to the word line select transistor.

Claims

1. An apparatus, comprising:

a memory cell array, wherein;

a memory element of a memory cell of the memory cell array is coupled to a source line of the memory cell array through a word line select transistor; and

a current limiting device is coupled between the source line and a supply voltage, the current limiting device to operate in a constant current mode during an access operation of the memory cell; and

an array control circuitry coupled to the memory cell array, the array control circuitry configured to control the constant current mode and supply an associated select bias voltage to the word line select transistor.

2. The apparatus of claim 1, wherein a source line of the memory cell array runs parallel to the bit line.

3. The apparatus of claim 1, wherein a source line of the memory cell array runs parallel to the word line.

4. The apparatus of claim 3, wherein the array control circuitry is configured to simultaneously select, for programming from a high resistance state to a low resistance state, another memory cell of the memory cell array.

5. The apparatus of claim 1, wherein the current limiting device comprises a pull-down transistor biased in saturation.

6. The apparatus of claim 5, wherein the array control circuitry comprises a diode configured stack of transistors, wherein a first transistor of the stack is selectably coupled to a gate of the word line select transistor and a second transistor of the stack is coupled to a gate of the pull-down transistor.

7. The apparatus of claim 6, wherein the diode configured stack of transistors comprises a diode configured stack of differently sized transistors.

8. The apparatus of claim 7, wherein a first size of the word line select transistor is less than a second size of the pull-down transistor.

9. The apparatus of claim 8, wherein a size of the first transistor of the stack corresponds to the first size, and wherein a size of the second transistor of the stack corresponds to the second size.

10. The apparatus of claim 1, wherein the memory element comprises a two terminal device.

11. A method, comprising:

selecting at least one memory cell of a memory array;

biasing a gate of a cell select transistor of the selected memory cell into saturation via a word line corresponding to the selected memory cell;

biasing a gate of a pull-down transistor that is coupled between a supply voltage and a source or drain of the cell select transistor into saturation; and

activating a bit line correspond to the selected memory cell to switch a memory element of the selected memory cell from a high resistance state to a low resistance state while the gates are biased into saturation.

12. The method of claim 11, wherein biasing the gate of the cell select transistor of the selected memory cell into saturation via the word line corresponding to the selected memory cell further comprises biasing the gate of the cell select transistor more than a threshold voltage above the gate of the pull-down transistor.

13. The method of claim 11, further comprising:

biasing at least one of a bit line or word line corresponding to an unselected memory cell of the memory cell differently than a respective one of the bit line or the word line of the selected memory cell to cause a memory element of the unselected memory cell to conduct less current than the memory element of the selected memory cell.

14. The method of claim 13, wherein the memory element of the unselected memory cell conducts no current.

15. An apparatus for operating a memory array, the apparatus comprising:

means for biasing a gate of a cell select transistor of a selected memory cell into saturation via a word line corresponding to the selected memory cell;

means for biasing a gate of a pull-down transistor that is coupled between a supply voltage and a source or drain of the cell select transistor into saturation; and

means for activating a bit line correspond to the selected memory cell to switch a memory element of the selected memory cell from a high resistance state to a low resistance state while the gates are biased into saturation.

16. The apparatus of claim 15, wherein the gate of the cell select transistor is biased more than a threshold voltage above the gate of the pull-down transistor.

17. The apparatus of claim 15, further comprising:

means for biasing at least one of a bit line or word line corresponding to an unselected memory cell of the memory cell differently than a respective one of the bit line or the word line of the selected memory cell to cause a memory element corresponding to the unselected memory cell to conduct less current than the memory element of the selected memory cell.

18. The apparatus of claim 17, wherein the memory element of the unselected memory cell conducts no current.