Self-storing and self-restoring non-volatile static random access memory
First Claim
1. An apparatus comprising:
- a Static Random Access Memory (SRAM) cell with at least two non-volatile (NV) resistive memory elements integrated within the SRAM cell; and
first logic to self-store data stored in the SRAM cell to the at least two NV resistive memory elements, wherein the first logic is to self-store the data by discharging voltages on both a bit-line and a complementary bit-line to ground.
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Accused Products
Abstract
An apparatus is provided which comprises: a Static Random Access Memory (SRAM) cell with at least two non-volatile (NV) resistive memory elements integrated within the SRAM cell; and first logic to self-store data stored in the SRAM cell to the at least two NV resistive memory elements. A method is provided which comprises performing a self-storing operation, when a voltage applied to a SRAM cell decreases to a threshold voltage, to store voltage states of the SRAM cell to at least two NV resistive memory elements, wherein the at least two NV resistive memory elements are integrated with the SRAM cell; and performing self-restoring operation, when the voltage applied to the SRAM cell increases to the threshold voltage, by copying data from the at least two NV resistive memory elements to storage nodes of the SRAM cell.
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Citations
23 Claims
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1. An apparatus comprising:
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a Static Random Access Memory (SRAM) cell with at least two non-volatile (NV) resistive memory elements integrated within the SRAM cell; and first logic to self-store data stored in the SRAM cell to the at least two NV resistive memory elements, wherein the first logic is to self-store the data by discharging voltages on both a bit-line and a complementary bit-line to ground. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A system comprising:
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a processor; a memory coupled to the processor, the memory including; a Static Random Access Memory (SRAM) cell with at least two non-volatile (NV) resistive memory elements integrated within the SRAM cell; and first logic to self-store data stored in the SRAM cell to the at least two NV resistive memory elements, wherein the first logic is to self-store the data by discharging voltages on both a bit-line and a complementary bit-line to ground; and a wireless interface for allowing the processor to communicate with another device. - View Dependent Claims (19)
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20. A method comprising:
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performing a self-storing operation, when a voltage applied to a Static Random Access Memory (SRAM) cell decreases to a threshold voltage, to store voltage states of the SRAM cell to at least two non-volatile (NV) resistive memory elements, wherein the at least two NV resistive memory elements are integrated with the SRAM cell; and performing self-restoring operation, when the voltage applied to the SRAM cell increases to the threshold voltage, by copying data from the at least two NV resistive memory elements to storage nodes of the SRAM cell, wherein performing the self-storing operation comprises setting bit-line and complementary bit-line associated with the SRAM cell to ground. - View Dependent Claims (21, 22, 23)
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Specification