Nonvolatile semiconductor memory device

• US 9,437,307 B2
• Filed: 10/13/2014
• Issued: 09/06/2016
• Est. Priority Date: 09/22/2010
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Itagaki, Kiyotaro, Kito, Masaru, Ogiwara, Ryu, Iwai, Hitoshi
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US14/512,940
• Publication Number:
  US 20150029791A1
• Time in Patent Office: 694 Days
• Field of Search: 365/185.18, 365/185.29, 365/185.3, 365/218
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.

Claims

1. A nonvolatile semiconductor memory device comprising:

a memory cell array including a plurality of memory strings, the memory strings including a first memory string and a second memory string, the first memory string and the second memory string being electrically connected to a first bit line,

the first memory string including a first memory cell, a second memory cell, a first selection transistor, and a second selection transistor, the first selection transistor being electrically connected to the first memory cell in series, the second selection transistor being electrically connected to the second memory cell in series,

the second memory string including a third memory cell, a fourth memory cell, a third selection transistor, and a fourth selection transistor, the third selection transistor being electrically connected to the third memory cell in series, the fourth selection transistor being electrically connected to the fourth memory cell in series, and

a controller configured to perform an erase operation for the first memory string or the second memory string separately.

2. The device according to claim 1, wherein gates of the first memory cell and the third memory cell are electrically connected, and gates of the second memory cell and the fourth memory cell are electrically connected.

3. The device according to claim 2, further comprising:

a plurality of source lines including a first source line and a second source line, the first memory string being electrically connected to the first source line, and the second memory string being electrically connected to the second source line.

4. The device according to claim 3, wherein:

the controller is configured to perform the erase operation for the first sting on a condition that a first voltage is applied to the first source line, a second voltage is applied to the second source line, and the first voltage is higher than the second voltage.

5. The device according to claim 3, wherein:

the memory strings include a third memory string and a fourth memory string, the third memory string and the fourth memory string being electrically connected to a second bit line,

the third memory string including a fifth memory cell, a sixth memory cell, a fifth selection transistor, and a sixth selection transistor, the fifth selection transistor being electrically connected to the fifth memory cell in series, the sixth selection transistor being electrically connected to the sixth memory cell in series,

the fourth memory string including a seventh memory cell, an eight memory cell, a seventh selection transistor, and an eighth selection transistor, the seventh selection transistor being electrically connected to the seventh memory cell in series, the eighth selection transistor being electrically connected to the eighth memory cell in series,

wherein the controller is configured to perform the erase operation for the first memory string and the third memory string without performing the erase operation for the second memory string and the fourth memory string.

6. The device according to claim 5, wherein gates of the first memory cell, the third memory cell, the fifth memory cell, and the seventh memory cell are electrically connected, and gates of the second memory cell, the fourth memory cell, the sixth memory cell, and the eighth memory cell are electrically connected.

7. The device according to claim 5, wherein:

the third memory string is electrically connected to the first source line, and the fourth memory string is electrically connected to the second source line.

8. The device according to claim 5, wherein the first memory cell, the third memory cell, the fifth memory cell, and the seventh memory cell are provided above the second memory cell, the fourth memory cell, the sixth memory cell, and the eighth memory cell.

9. The device according to claim 5, wherein gates of the first selection transistor and the fifth selection transistor are electrically connected, gates of the first selection transistor and the fifth selection transistor are electrically connected.

10. The device according to claim 1, wherein the first memory cell is provided above the second memory cell.

11. The device according to claim 1, wherein the first memory cell includes a charge storage layer.