Self-aligned trench isolation in integrated circuits

• US 9,437,470 B2
• Filed: 10/08/2013
• Issued: 09/06/2016
• Est. Priority Date: 10/08/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Lu, Ching-Huang, Xue, Lei, Ohtsuka, Kenichi, Chan, Simon Siu-Sing, Sugino, Rinji
• Primary Examiner(s): Sarkar, Asok K
• Assistant Examiner(s): WITHERS, GRANT S
• Application Number:
  US14/048,863
• Publication Number:
  US 20150097245A1
• Time in Patent Office: 1,064 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.

Claims

1. An integrated circuit (IC) comprising:

a substrate;

first and second devices having;

respective first and second gate structures,

respective first and second doped regions; and

a trench in the substrate self-aligned between the first and second gate structures, the trench comprising;

a first filled portion comprising a dielectric material configured to form a buried trench isolation between the first and second devices; and

a second filled portion comprising a conductive material, wherein a top surface of the second filled portion is substantially coplanar with a top surface of the substrate,

wherein the first and second doped regions are substantially in contact with at least a part of the second filled portion.

2. The IC of claim 1, wherein a top surface of the first filled portion is substantially in contact with a bottom surface of the second filled portion.

3. The IC of claim 1, wherein at least one of the first and second gate structures comprises:

a dielectric layer comprising a silicon oxide layer or a high-k dielectric layer, the dielectric layer being disposed on the top surface of the substrate; and

a gate layer comprising a polycrystalline silicon layer or a metal layer, the gate layer being disposed on the dielectric layer.

4. The IC of claim 1, wherein at least one of the first and second gate structures comprises:

a dielectric layer comprising a silicon oxide layer or a high-k dielectric layer, the dielectric layer being disposed on the top surface of the substrate; and

a first and second gate layer, each of the first and second gate layers comprising a polycrystalline silicon layer or a metal layer.

5. The IC of claim 4, wherein:

the first gate layer is disposed on the dielectric layer; and

the second gate layer is disposed on the first gate layer.

6. The IC of claim 1, wherein at least one of the first and second gate structures comprises:

a charge storing layer disposed between a first dielectric layer and a second dielectric layer, the first dielectric layer being disposed on the top surface of the substrate; and

a gate layer comprising a polycrystalline silicon layer or a metal layer, the gate layer being disposed on the second dielectric layer.

7. The IC of claim 6, wherein:

the charge storing layer comprises a nitride layer or a polycrystalline silicon layer; and

each of the first and second dielectric layers comprises an oxide layer.

8. An integrated circuit (IC) comprising:

a substrate;

first and second devices each having a doped region; and

a trench in the substrate self-aligned between the first and second devices, the trench comprising;

a first filled portion comprising a dielectric material configured to electrically isolate the first and second devices; and

a second filled portion comprising a conductive material,

wherein the doped regions are substantially in contact with at least a part of the second filled portion.

9. The IC of claim 8, wherein a top surface of the first filled portion is substantially in contact with a bottom surface of the second filled portion.

10. The IC of claim 8, wherein at least one of the first and second devices further comprises a gate structure, the gate structure comprising:

a dielectric layer comprising a silicon oxide layer or a high-k dielectric layer, the dielectric layer being disposed on a top surface of the substrate; and

a gate layer comprising a polycrystalline silicon layer or a metal layer, the gate layer being disposed on the dielectric layer.

11. The IC of claim 8, wherein at least one of the first and second devices further comprises a gate structure, the gate structure comprising:

a dielectric layer comprising a silicon oxide layer or a high-k dielectric layer, the dielectric layer being disposed on a top surface of the substrate; and

a first and second gate layer, each of the first and second gate layers comprising a polycrystalline silicon layer or a metal layer.

12. The IC of claim 11, wherein:

the first gate layer is disposed on the dielectric layer; and

the second gate layer is disposed on the first gate layer.

13. The IC of claim 8, wherein at least one of the first and second devices further comprises a gate structure, the gate structure comprising:

a charge storing layer disposed between a first dielectric layer and a second dielectric Layer, the first dielectric layer being disposed on a top surface of the substrate; and

a gate layer comprising a polycrystalline silicon layer or a metal layer, the gate layer being disposed on the second dielectric layer.

14. The IC of claim 13, wherein:

the charge storing layer comprises a nitride layer or a polycrystalline silicon layer; and

each of the first and second dielectric layers comprises an oxide layer.