Substrate for semiconductor package and process for manufacturing

• US 9,437,532 B2
• Filed: 12/16/2015
• Issued: 09/06/2016
• Est. Priority Date: 07/05/2012
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Chen, Tien-Szu, Lee, Chun-Che, Wang, Sheng-Ming
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US14/971,165
• Publication Number:
  US 20160104667A1
• Time in Patent Office: 265 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/48 Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2224/13005 Structure
• CPC Class Codes: H01L 2224/13013 being rectangular or square
• CPC Class Codes: H01L 2224/13016 in side view
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/16055 being circular or elliptic
• CPC Class Codes: H01L 2224/16057 in side view
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/3142 : Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H05K 2201/0367 : Metallic bump or raised conductor not used as solder bump solder materials or compositions and methods of application thereof H05K3/3457
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457

Abstract

A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

Claims

1. A semiconductor package, comprising:

a package substrate comprising;

a dielectric layer;

a first circuit layer disposed on or in the dielectric layer; and

a plurality of pillars disposed on the first circuit layer, wherein each of the pillars has a recess portion in the top end of the pillar;

a die; and

a plurality of solder balls disposed on the die, wherein each of the solder balls is bonded to each of the pillars and kept at the recess portion.

2. The semiconductor package of claim 1, further comprising an insulation material enclosing the pillars.

3. The semiconductor package of claim 1, wherein the first circuit layer is embedded in the dielectric layer.

4. The semiconductor package of claim 1, wherein each of the pillars has a top surface adapted for making external electrical connection, and a coplanarity of the top surfaces of the pillars is ±

3 μ

m.

5. The semiconductor package of claim 1, wherein the recess portion is disposed at the periphery of the top end of the pillar, and a cross section of the recess portion has a concave profile.

6. The semiconductor package of claim 1, wherein a width of the top end of the pillar is less than that of a bottom end of the pillar.

7. A semiconductor package, comprising:

a dielectric layer;

a first circuit layer disposed on or in the dielectric layer;

a plurality of pillars disposed on the first circuit layer, wherein each of the pillars has a recess portion in the top end of the pillar;

an insulation material enclosing the pillars;

a die attached to the pillars; and

a molding compound encapsulating the die.

8. The semiconductor package of claim 7, wherein the insulation material is an underfill.

9. The semiconductor package of claim 7, wherein the first circuit layer is embedded in the dielectric layer.

10. The semiconductor package of claim 7, wherein each of the pillars has a top surface adapted for making external electrical connection, and a coplanarity of the top surfaces of the pillars is ±

3 μ

m.

11. The semiconductor package of claim 7, further comprising a protection layer disposed on the first circuit layer, the protection layer has an opening to expose a portion of the first circuit layer and the pillars.

12. The semiconductor package of claim 11, wherein the pillars extend from the first circuit layer and beyond the protection layer.

13. The semiconductor package of claim 7, wherein the recess portion is disposed at the periphery of the top end of the pillar, and a cross section of the recess portion has a concave profile.

14. The semiconductor package of claim 7, wherein a width of the top end of the pillar is less than that of a bottom end of the pillar.

15. A process for making a package substrate, comprising:

(a) providing a package substrate, wherein the package substrate includes a dielectric layer and a first circuit layer disposed on or in the dielectric layer;

(b) forming a photoresist pattern adjacent to the first circuit layer, wherein the photoresist pattern has a plurality of openings;

(c) forming a plurality of pillars in the openings of the photoresist pattern; and

(d) removing a part of each of the top ends of the pillar so that each of the pillars has a recess portion in the top end of the pillar.

16. The process of claim 15, wherein after (c), the process further comprises:

(c1) forming a top photoresist layer on a central part of each of the top surfaces of the pillars.

17. The process of claim 16, wherein in (d), the recess portion is formed at a periphery of the top end of the pillar, and a cross section of the recess portion has a concave profile.

18. The process of claim 16, wherein in (d), a space is formed between a side surface of the top end of the pillar and a side wall of the opening of the photoresist pattern.

19. The process of claim 15, wherein in (c), the pillar protrudes from the top surface of photoresist pattern and covers a part of the top surface of the photoresist pattern.

20. The process of claim 19, wherein in (d), the part of the pillar which covers the part of the top surface of the photoresist pattern is removed by etching.