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Temperature compensation method for high-density floating-gate memory

  • US 9,437,602 B2
  • Filed: 11/27/2012
  • Issued: 09/06/2016
  • Est. Priority Date: 12/02/2011
  • Status: Active Grant
First Claim
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1. A non-volatile memory arrangement, comprising:

  • a first memory circuit having a floating gate transistor with a gate node and operating in weak-inversion mode, and a varactor with first terminal electrically coupled to the gate node of the floating gate transistor; and

    a control module electrically coupled to a second terminal of the varactor and operable to tune a voltage applied to the varactor, thereby compensating for temperature changes, wherein the first memory circuit further includes a tunneling capacitor coupled electrically to the gate node of the floating gate transistor and a control-gate capacitor coupled electrically to the gate node of the floating gate transistor, wherein the tunneling capacitor configured to receive an injection current for the first memory circuit.

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