Temperature compensation method for high-density floating-gate memory
First Claim
1. A non-volatile memory arrangement, comprising:
- a first memory circuit having a floating gate transistor with a gate node and operating in weak-inversion mode, and a varactor with first terminal electrically coupled to the gate node of the floating gate transistor; and
a control module electrically coupled to a second terminal of the varactor and operable to tune a voltage applied to the varactor, thereby compensating for temperature changes, wherein the first memory circuit further includes a tunneling capacitor coupled electrically to the gate node of the floating gate transistor and a control-gate capacitor coupled electrically to the gate node of the floating gate transistor, wherein the tunneling capacitor configured to receive an injection current for the first memory circuit.
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Accused Products
Abstract
A temperature compensation technique is provided for a non-volatile memory arrangement. The memory arrangement includes: a memory circuit (12) having a floating gate transistor (P3) operating in weak-inversion mode and a varactor (Cv) with a terminal electrically coupled to a gate node of the floating gate transistor; a first current reference circuit (14) having a floating gate transistor (PI); a second current reference circuit (16) having a floating gate transistor (P2); and a control module (18) configured to selectively receive a reference current (I1, I2) from a drain of the floating gate transistor in each of the first and second current reference circuits. The control module operates to determine a ratio between the reference currents received from the first and second current reference circuits, generate a tuning voltage (Vx) in accordance with the ratio between the reference currents and apply the tuning voltage to the varactor in the memory circuit.
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Citations
16 Claims
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1. A non-volatile memory arrangement, comprising:
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a first memory circuit having a floating gate transistor with a gate node and operating in weak-inversion mode, and a varactor with first terminal electrically coupled to the gate node of the floating gate transistor; and a control module electrically coupled to a second terminal of the varactor and operable to tune a voltage applied to the varactor, thereby compensating for temperature changes, wherein the first memory circuit further includes a tunneling capacitor coupled electrically to the gate node of the floating gate transistor and a control-gate capacitor coupled electrically to the gate node of the floating gate transistor, wherein the tunneling capacitor configured to receive an injection current for the first memory circuit. - View Dependent Claims (2)
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3. A non-volatile memory arrangement, comprising:
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a first memory circuit having a floating gate transistor with a gate node and operating in weak-inversion mode, and a varactor with first terminal electrically coupled to the gate node of the floating gate transistor; a first current reference circuit and a second current reference circuit, the first and second current reference circuit each having a floating gate transistor operating in a weak-inversion mode and a varactor having a first terminal electrically coupled to a gate node of the floating gate transistor; and a control module electrically coupled to a second terminal of the varactor and operable to tune a voltage applied to the varactor, thereby compensating for temperature changes. - View Dependent Claims (4, 5, 6, 7)
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8. A non-volatile memory arrangement, comprising:
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a first memory circuit having a floating gate transistor with a gate node and operating in weak-inversion mode, and a varactor with a first terminal electrically coupled to the gate node of the floating gate transistor; a first current reference circuit having a floating gate transistor operating in a weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor; a second current reference circuit having a floating gate transistor operating in a weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor; and a control module configured to selectively receive a reference current from a drain of the floating gate transistor in each of the first and second current reference circuits and determine a ratio between the reference currents received from the first and second current reference circuits, the control module further operates to generate a tuning voltage that maintains the ratio between the reference currents constant and applies the tuning voltage to a second terminal of the varactor in the first memory circuit. - View Dependent Claims (9, 10, 11, 12)
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13. A non-volatile memory arrangement comprising:
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an array of memory circuits, each memory circuit having a floating gate transistor operating in weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor; a first current reference circuit having a floating gate transistor operating in a weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor; a second current reference circuit having a floating gate transistor operating in a weak-inversion mode and a varactor with a first terminal electrically coupled to a gate node of the floating gate transistor; and a control module configured to selectively receive a reference current from a drain of the floating gate transistor in each of the first and second current reference circuits and determine a ratio between the reference currents received from the first and second current reference circuits, the control module further operates to generate a tuning voltage in accordance with the ratio between the reference currents and applies the tuning voltage to the varactor of each memory circuit in the array of memory circuits. - View Dependent Claims (14, 15, 16)
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Specification