High-density power MOSFET with planarized metalization

• US 9,437,729 B2
• Filed: 01/08/2007
• Issued: 09/06/2016
• Est. Priority Date: 01/08/2007
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Li, Jian
• Primary Examiner(s): Payen, Marvin
• Application Number:
  US11/651,258
• Publication Number:
  US 20080164515A1
• Time in Patent Office: 3,529 Days
• Field of Search: 257/329, 257/330, 438/272, 438/586
• US Class Current: 1/1
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A method for producing a power MOSFET. The method includes fabricating a plurality of layers of a power MOSFET to produce an upper surface active area and performing a chemical mechanical polishing process on the active area to produce a substantially planar surface. A metalization deposition process is then performed on the substantially planar surface and the fabrication of the power MOSFET is subsequently completed.

Claims

1. A method for producing a power MOSFET, comprising:

fabricating a plurality of layers of a power MOSFET and an integrated Schottky device to produce an upper surface active area;

performing a chemical mechanical polishing process on the upper surface active area to produce a substantially planar surface, wherein a gate contact is coplanar with an oxide deposit, wherein the oxide deposit comprises a source region, and wherein the oxide deposit comprises a drain region;

performing a metalization deposition process on the substantially planar surface, wherein a portion of the metallization deposition is in contact with the gate contact; and

completing fabrication of the power MOSFET and Schottky device.

2. The method of claim 1 wherein the active area comprises silicon dioxide sub-areas and tungsten sub-areas.

3. The method of claim 2 wherein the chemical mechanical polishing process comprises a tungsten optimized process.

4. The method of claim 1 wherein the metalization deposition is configured to deposit a metal layer less than 4 microns deep.

5. The method of claim 4 wherein the metal layer is configured to accept a plurality of wire bonds for completing fabrication of the power MOSFET.

6. The method of claim 1 wherein the power MOSFET is a high density power MOSFET.

7. A method for producing a high density power MOSFET, comprising:

fabricating a plurality of layers of a power MOSFET and an integrated Schottky device to produce an upper surface active area;

performing a chemical mechanical polishing process on the upper surface active area to produce a substantially planar surface, wherein a gate contact is coplanar with an oxide deposit, wherein the oxide deposit comprises a source region, and wherein the oxide deposit comprises a drain region;

performing a metalization deposition process on the substantially planar surface, wherein the metalization deposition is configured to deposit a metal layer less than 4 microns deep, wherein a portion of the metallization deposition is in contact with the gate contact; and

completing fabrication of the power MOSFET and Schottky device.

8. The method of claim 7 wherein the active area comprises silicon dioxide sub-areas and tungsten sub-areas.

9. The method of claim 8 wherein the chemical mechanical polishing process comprises a tungsten optimized process.

10. The method of claim 7 wherein the metalization deposition is configured to deposit a metal layer less than 2 microns deep.

11. The method of claim 10 wherein the metal layer is configured to accept a plurality of wire bonds for completing fabrication of the power MOSFET.

12. The method of claim 7 wherein the upper surface of the active area is a high aspect ratio surface.

13. The method of claim 7 wherein the power MOSFET is an N channel device or a P channel device.

14. The method of claim 7 wherein the integrated Schottky device comprises a region larger than a gate contact region of the power MOSFET.

15. The method of claim 10 wherein the upper surface of the active area is a high aspect ratio surface, and wherein the power MOSFET is an N channel device or a P channel device, and wherein the integrated Schottky device comprises a region larger than a source contact region of the power MOSFET.