Semiconductor device and method for manufacturing same

• US 9,437,745 B2
• Filed: 01/22/2013
• Issued: 09/06/2016
• Est. Priority Date: 01/26/2012
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Saitoh, Yuhichi
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Newton, Valerie N
• Application Number:
  US14/373,620
• Publication Number:
  US 20140361294A1
• Time in Patent Office: 1,323 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The present invention provides a semiconductor device which is provided with an oxide semiconductor TFT that can be reduced in the parasitic capacitance by suppressing process damage to a channel, while reducing the channel length (L). A semiconductor device of the present invention is provided with: a gate electrode (3) that is provided on a substrate (1); a first insulating layer (5) that is formed on the gate electrode (3); an island-shaped oxide semiconductor layer (7) that is formed on the first insulating layer (5); a source electrode (11) and a drain electrode (13) that are electrically connected to the oxide semiconductor layer (7); and a protective layer (9) that covers the upper surface of the oxide semiconductor layer (7). The source electrode (11) and/or the drain electrode (13) is arranged on a portion of the side faces of the oxide semiconductor layer (7) and a portion of the side faces of the protective layer (9), but does not cover the upper face of the protective layer (9).

Claims

1. A semiconductor device, comprising:

a substrate;

a gate electrode provided on the substrate;

a first insulating layer formed on the gate electrode;

an island-shaped oxide semiconductor layer formed on the first insulating layer;

a source electrode electrically connected to the oxide semiconductor layer;

a drain electrode electrically connected to the oxide semiconductor layer; and

a protective layer covering an upper face of the oxide semiconductor layer,

wherein at least one of the source electrode and the drain electrode is disposed on a portion of side faces of the oxide semiconductor layer and on a portion of side faces of the protective layer, and does not cover an upper face of the protective layer, and

wherein the side faces of the oxide semiconductor layer include a first side face that has a first taper angle and a second side face that has a second taper angle that is smaller than the first taper angle, and said at least one of the source electrode and the drain electrode is formed on said first side face of the oxide semiconductor layer but is not formed on said second side face, said first taper angle being greater than or equal to 70 degrees and less than 90 degrees and said second taper angle being greater than or equal to 45 degrees and less than 70 degrees.

2. The semiconductor device according to claim 1, wherein an upper edge face of said at least one of the source electrode and the drain electrode is flush with the upper face of the protective layer.

3. The semiconductor device according to claim 1, wherein said at least one of the source electrode and the drain electrode is in contact with the oxide semiconductor layer only at the side faces of the oxide semiconductor layer.

4. The semiconductor device according to claim 1, wherein a portion of the side faces of the oxide semiconductor layer is flush with a portion of the side faces of the protective layer.

5. The semiconductor device according to claim 1, wherein said oxide semiconductor layer includes an In—

Ga—

Zn—

O semiconductor.