Semiconductor device and method for fabricating the same

• US 9,437,749 B2
• Filed: 01/14/2016
• Issued: 09/06/2016
• Est. Priority Date: 08/10/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): SHOOK, DANIEL P
• Application Number:
  US14/995,247
• Publication Number:
  US 20160133756A1
• Time in Patent Office: 236 Days
• Field of Search: 257/43, 438/104
• US Class Current: 1/1
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

To provide a highly reliable semiconductor device exhibiting stable electrical characteristics. To fabricate a highly reliable semiconductor device. Included are an oxide semiconductor stack in which a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are stacked, a source and a drain electrode layers contacting the oxide semiconductor stack, a gate electrode layer overlapping with the oxide semiconductor layer with a gate insulating layer provided therebetween, and a first and a second oxide insulating layers between which the oxide semiconductor stack is sandwiched. The first to the third oxide semiconductor layers each contain indium, gallium, and zinc. The proportion of indium in the second oxide semiconductor layer is higher than that in each of the first and the third oxide semiconductor layers. The first oxide semiconductor layer is amorphous. The second and the third oxide semiconductor layers each have a crystalline structure.

Claims

1. A semiconductor device comprising:

a transistor including a channel formation region, the channel formation region comprising silicon,

a first insulating layer over the transistor,;

a first gate electrode over the first insulating layer;

a second insulating layer over the first gate electrode;

a first oxide semiconductor layer over the second insulating layer, the first oxide semiconductor layer overlapping with the first gate electrode;

a second oxide semiconductor layer over the first oxide semiconductor layer, the second oxide semiconductor layer overlapping with the first gate electrode;

a third oxide semiconductor layer over the second oxide semiconductor layer, the third oxide semiconductor layer overlapping with the first gate electrode;

a source electrode and a drain electrode over the first oxide semiconductor layer and the second oxide semiconductor layer, the source electrode and the drain electrode electrically connected to the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer;

a third insulating layer over the third oxide semiconductor layer, the source electrode, and the drain electrode; and

a second gate electrode over the third insulating layer, the second gate electrode overlapping with the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer,

wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises at least one of indium, zinc, and gallium,

wherein the third oxide semiconductor layer and a side surface of the second oxide semiconductor layer are in contact with each other, and

wherein the third oxide semiconductor layer and a side surface of the first oxide semiconductor layer are in contact with each other.

2. The semiconductor device according to claim 1, wherein the first insulating layer comprises aluminum and oxygen.

3. The semiconductor device according to claim 1, wherein each of the second oxide semiconductor layer and the third oxide semiconductor layer has a crystalline structure.

4. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer has an amorphous structure.

5. The semiconductor device according to claim 1, wherein a composition of the second oxide semiconductor layer and a composition of the third oxide semiconductor layer are different from each other.

6. The semiconductor device according to claim 1, wherein the second insulating layer contains oxygen in excess of a stoichiometric composition.

7. The semiconductor device according to claim 1, wherein a concentration of silicon or carbon in each of the first oxide semiconductor layer and the third oxide semiconductor layer is lower than or equal to 3×

10¹⁸ atoms/cm³.

8. The semiconductor device according to claim 1, wherein each of the source electrode and the drain electrode is in contact with the second insulating layer.

9. The semiconductor device according to claim 1, wherein the source electrode and the drain electrode is positioned over the third oxide semiconductor layer.

10. A semiconductor device comprising:

a transistor including a channel formation region, the channel formation region comprising silicon,

a first insulating layer over the transistor;

a first gate electrode over the first insulating layer;

a second insulating layer over the first gate electrode;

a first oxide semiconductor layer over the second insulating layer, the first oxide semiconductor layer overlapping with the first gate electrode;

a second oxide semiconductor layer over the first oxide semiconductor layer, the second oxide semiconductor layer overlapping with the first gate electrode;

a third oxide semiconductor layer over the second oxide semiconductor layer, the third oxide semiconductor layer overlapping with the first gate electrode;

a source electrode and a drain electrode over the first oxide semiconductor layer and the second oxide semiconductor layer, the source electrode and the drain electrode electrically connected to the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer;

a third insulating layer over the third oxide semiconductor layer, the source electrode, and the drain electrode; and

a second gate electrode over the third insulating layer, the second gate electrode overlapping with the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer,

wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer comprises at least one of indium, zinc, and gallium,

wherein the third oxide semiconductor layer and a side surface of the second oxide semiconductor layer are in contact with each other,

wherein the third oxide semiconductor layer and a side surface of the first oxide semiconductor layer are in contact with each other, and

wherein one of the source electrode and the drain electrode is electrically connected to the transistor.

11. The semiconductor device according to claim 10, wherein the first insulating layer comprises aluminum and oxygen.

12. The semiconductor device according to claim 10, wherein each of the second oxide semiconductor layer and the third oxide semiconductor layer has a crystalline structure.

13. The semiconductor device according to claim 10, wherein the first oxide semiconductor layer has an amorphous structure.

14. The semiconductor device according to claim 10, wherein a composition of the second oxide semiconductor layer and a composition of the third oxide semiconductor layer are different from each other.

15. The semiconductor device according to claim 10, wherein the second insulating layer contains oxygen in excess of a stoichiometric composition.

16. The semiconductor device according to claim 10, wherein a concentration of silicon or carbon in each of the first oxide semiconductor layer and the third oxide semiconductor layer is lower than or equal to 3×

10¹⁸ atoms/cm3.

17. The semiconductor device according to claim 10, wherein each of the source electrode and the drain electrode is in contact with the second insulating layer.

18. The semiconductor device according to claim 10, wherein the source electrode and the drain electrode is positioned over the third oxide semiconductor layer.