Extreme ultraviolet lithography process and mask
First Claim
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1. An extreme ultraviolet lithography (EUVL) process, comprising:
- providing a patterned mask including a phase-defect region;
receiving information of a position of diffraction light (PDL), diffracted from the patterned mask on a pupil plane of a projection optics box (POB);
exposing the patterned mask by an on-axis illumination (ONI) with partial coherence σ
less than 0.3;
utilizing a pupil filter to control light intensity distribution diffracted from the patterned mask, the pupil filter including;
a light-transmitting region defined by the PDL; and
rest of areas of the pupil filter set to be an opaque region;
compensating, by the pupil filter, for a phase error caused by the phase-defect region at a time of exposure of the patterned mask; and
collecting and directing the diffracted light from the patterned mask to expose a target.
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Abstract
The present disclosure is directed towards lithography processes. In one embodiment, a patterned mask is provided. An information of a position of diffraction light (PDL) on a pupil plane of a projection optics box (POB) is used to define as a light-transmitting region of a pupil filter. The patterned mask is exposed by an on-axis illumination (ONI) with partial coherence σ less than 0.3. The pupil filter is used to transmit diffraction light to a target.
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Citations
20 Claims
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1. An extreme ultraviolet lithography (EUVL) process, comprising:
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providing a patterned mask including a phase-defect region; receiving information of a position of diffraction light (PDL), diffracted from the patterned mask on a pupil plane of a projection optics box (POB); exposing the patterned mask by an on-axis illumination (ONI) with partial coherence σ
less than 0.3;utilizing a pupil filter to control light intensity distribution diffracted from the patterned mask, the pupil filter including; a light-transmitting region defined by the PDL; and rest of areas of the pupil filter set to be an opaque region; compensating, by the pupil filter, for a phase error caused by the phase-defect region at a time of exposure of the patterned mask; and collecting and directing the diffracted light from the patterned mask to expose a target. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An extreme ultraviolet lithography (EUVL) process, comprising:
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receiving a mask for EUVL, the mask includes; a substrate including a first region and a second region; a multilayer mirror above the first and second regions; an absorption layer above the multilayer mirror in the second region; and a resultant phase-defect region in the first region; providing information of a position of diffraction light (PDL), diffracted from the mask on a pupil plane of a projection optics box (POB); exposing the mask by an on-axis illumination (ONI) with partial coherence σ
less than 0.3;utilizing a pupil filter to control light intensity distribution diffracted from the mask, the pupil filter including; a light-transmitting region defined by the PDL; and rest of areas of the pupil filter set to be an opaque region, wherein the pupil filter compensates for the resultant phase-defect region at a time of exposure of the mask; and collecting and directing the diffracted light from the patterned mask to expose a target. - View Dependent Claims (10, 11, 12, 13)
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14. An extreme ultraviolet lithography (EUVL) system, comprising:
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a patterned mask having one dimensional patterns, the patterned mask including a phase-defect region; a dipole illumination with partial coherence σ
less than 0.3 for exposing the mask;a pupil filter having a light-transmitting region defined by a position of diffracted light (PDL) diffracted from the patterned mask on a pupil plane and an opaque region set to rest area of the pupil filter; and optics configured to collect diffracted light transmitted through the pupil filter and direct the diffracted light to expose a target, wherein the pupil filter compensates for the phase-defect region during the exposing of the patterned mask. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification