Memory system

• US 9,442,797 B2
• Filed: 05/21/2014
• Issued: 09/13/2016
• Est. Priority Date: 12/24/2013
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Shin, Beom Ju
• Primary Examiner(s): LAMARRE, GUY J
• Application Number:
  US14/283,954
• Publication Number:
  US 20150178156A1
• Time in Patent Office: 846 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1612 where the redundant component is persistent storage
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A memory system is provided. The memory system includes a memory device suitable for reading out data from memory cells by a plurality of read voltages having various levels, and a controller suitable for updating probabilistic information based on the read out data when the read out data is input to the controller, and performing an error correction operation by the updated probabilistic information, wherein the controller updates the probabilistic information a predetermined number of times that the memory device reads out the data.

Claims

1. A memory system comprising:

a memory device configured to read out normal data from memory cells, and read out sampling data including N units of sampling data from the memory cells by use of a plurality of read voltages, the N units of sampling data being output N times with one unit of sampling data per time, N being a natural number greater than 1; and

a controller configured to generate probabilistic information, and update the probabilistic information based on the sampling data input from the memory device, and configured to perform an error correction operation, to correct errors in the normal data, by use of the updated probabilistic information,

wherein the controller repeatedly updates the probabilistic information whenever at least one unit of the sampling data is input to the controller, and

the controller performs the error correction operation after the N units of sampling data are input from the memory device.

2. The memory system of claim 1, wherein the controller updates the probabilistic information based on a first unit of sampling data among the sampling data while the memory device reads out a second unit of sampling data among the sampling data from the memory cells.

3. The memory system of claim 1, wherein the controller further comprises a buffer configured to store the sampling data.

4. The memory system of claim 3, wherein the controller replaces a first unit of sampling data, among the sampling data, previously stored in the buffer with a second unit of sampling data, among the sampling data, read out currently.

5. The memory system of claim 1, wherein the controller comprises:

a probabilistic information generator configured to update the probabilistic information based on the sampling data when the memory device reads out the sampling data and provides the sampling data to the controller, and

an error correction block configured to perform the error correction operation by the probabilistic information updated by the probabilistic information generator.

6. The memory system of claim 5, wherein the probabilistic information generator comprises:

a sampling counter configured to generate a count value representing a number of times that the memory device provides the sampling data to the controller;

a probabilistic information lookup table configured to provide information for updating the probabilistic information in response to the count value;

a buffer configured to store the sampling data; and

a probabilistic information register configured to update the probabilistic information based on the sampling data stored in the buffer and the information provided from the probabilistic information lookup table.

7. The memory system of claim 6, wherein an amount of the information provided from the probabilistic information lookup table varies depending on the N times.

8. The memory system of claim 6, wherein the probabilistic information generator replaces a first unit of sampling data, among the sampling data, previously stored in the buffer with a second unit of sampling data, among the sampling data, read out currently.

9. The memory system of claim 1, wherein the memory device sequentially uses the read voltages in ascending order of voltage levels to read the sampling data from the memory cells.

10. The memory system of claim 1, wherein the memory device sequentially uses the read voltages in descending order of voltage levels to read the sampling data from the memory cells.

11. The memory system of claim 1, wherein the memory device reads the sampling data from the memory cells by use of the read voltages to distinguish a first threshold voltage distribution and a second threshold voltage distribution that are adjacent to each other.

12. A memory system comprising:

a storage unit configured to store sampling data input from a memory device;

a probabilistic information generator configured to generate probabilistic information, and update the probabilistic information based on the sampling data when the sampling data is stored in the storage unit; and

an error correction block configured to perform an error correction operation on normal data, input from the memory device, for correcting errors in the normal data by the updated probabilistic information,

wherein the probabilistic information generator updates the probabilistic information N times that the sampling data is input to the storage unit, N being a natural number greater than 1, and

the error correction block performs the error correction operation after the probabilistic information generator updates the probabilistic information N times.

13. The memory system of claim 12, wherein the probabilistic information generator updates the probabilistic information based on a first unit of sampling data among the sampling data while a second unit of sampling data among the sampling data is read from the memory device.

14. The memory system of claim 12, wherein a first unit of sampling data, among the sampling data, previously stored in the storage unit is replaced with a second unit of sampling data, among the sampling data, read out currently.

15. The memory system of claim 12, wherein the probabilistic information generator comprises:

a sampling counter configured to generate a count value representing a number of times that the sampling data is input to the storage unit;

a probabilistic information lookup table configured to provide information for updating the probabilistic information in response to the count value; and

a probabilistic information register configured to update the probabilistic information based on the sampling data stored in the storage unit and the information provided from the probabilistic information lookup table.

16. The memory system of claim 15, wherein an amount of the information provided from the probabilistic information lookup table varies depending on the N times.