Arithmetic processing device, information processing device, control method for information processing device, and control program for information processing device

• US 9,442,836 B2
• Filed: 08/21/2014
• Issued: 09/13/2016
• Est. Priority Date: 09/20/2013
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yamamura, Shuji, Maruyama, Masaharu, Yoshida, Toshio, Kan, Ryuji, Kiyota, Naohiro, Hondo, Mikio, Motokurumada, Tsuyoshi
• Primary Examiner(s): THAI, TUAN V
• Application Number:
  US14/464,808
• Publication Number:
  US 20150089180A1
• Time in Patent Office: 754 Days
• Field of Search: 711/100, 711/154, 711/170
• US Class Current: 1/1
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 12/1483 using an access-table, e.g. matrix or list
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction

Abstract

An arithmetic processing device having an allocation unit configured to reserve a memory allocation area in a memory and register address range information indicating an address range of the memory allocation area in an address range table, in response to an execution of a memory area allocation function requesting memory area allocation, and a determination unit configured to refer to the address range table and perform determination processing as to whether or not an access destination address of a memory access instruction is within an address range indicated by the address range information registered in the address range table, in response to an execution of the memory access instruction relating to the memory allocation area.

Claims

1. An arithmetic processing device comprising:

an allocation unit configured to reserve a memory allocation area in a memory and register address range information indicating an address range of the memory allocation area and management area identification information identifying a memory area allocation function in an address range table, in response to an execution of the memory area allocation function requesting memory area allocation;

a determination unit configured to refer to the address range table and perform determination processing as to whether or not an access destination address of a memory access instruction is within an address range indicated by the address range information that is registered in the address range table and that corresponds to the management area identification information of the memory access instruction, in response to an execution of the memory access instruction;

the allocation unit configured to register any management area identification information amongst a first management area identification information group, together with the address range information, in the address range table, in response to the execution of the memory area allocation function that requires an address range check, and configured to register second management area identification information that is distinguished from the first management area identification information group, together with the address range information, in the address range table, in response to the execution of the memory area allocation function that does not require the address range check; and

the determination unit does not determine that the access destination address is outside the address range, regardless of the determination as to whether or not the access destination address is within the address range indicating the address range information registered in the address range table, when the management area identification information held by the memory access instruction is the second management area identification information, in response to the execution of the memory access instruction.

2. The arithmetic processing device according to claim 1, further comprising:

an address translation unit configured to, in response to an execution of a memory access instruction, refer to an address translation reference table, which translates an access destination address of the memory access instruction into a physical address, and output a physical address corresponding to the access destination address, wherein

the determination unit and the address translation unit are provided at the same pipeline stage; and

the address translation unit is configured to refer to the address translation reference table while ignoring the management area identification information in the access destination address when an address range check mechanism is set to be operable, and refer to the address translation reference table, without ignoring the management area identification information in the access destination address, when the address range check mechanism is set to be inoperable.

3. An arithmetic processing device comprising:

an allocation unit configured to reserve a memory allocation area in a memory and register address range information indicating an address range of the memory allocation area in an address range table, in response to an execution of a memory area allocation function requesting memory area allocation;

a determination unit configured to refer to the address range table and perform determination processing as to whether or not an access destination address of a memory access instruction is within an address range indicated by the address range information registered in the address range table, in response to an execution of the memory access instruction; and

an address translation unit configured to, in response to the execution of the memory access instruction, refer to an address translation reference table, which translates an access destination address of the memory access instruction into a physical address, and output a physical address corresponding to the access destination address, wherein

the determination unit and the address translation unit are provided at the same pipeline stage.

4. An arithmetic processing device comprising:

an allocation unit configured to reserve a memory allocation area in a memory and register address range information indicating an address range of the memory allocation area in an address range table, in response to an execution of a memory area allocation function requesting memory area allocation;

a determination unit configured to refer to the address range table and perform determination processing as to whether or not an access destination address of a memory access instruction is within an address range indicated by the address range information registered in the address range table, in response to an execution of the memory access instruction; and

a cache configured to have a cache memory and a cache pipeline, wherein

the address range table is stored in the memory;

the determination unit includes an address range register which is provided in the cache pipeline and in which address range information on a predetermined number of elements in the address range table is registered, and

the determination processing includes a first determination performed with reference to the address range register, and a second determination performed with reference to the address range table when the access destination address is determined not to be within an address range indicated by address range information registered in the address range register, in the first determination.

5. The arithmetic processing device according to claim 4, wherein the determination unit is configured to cause an operation system to execute the second determination.

6. The arithmetic processing device according to claim 4, wherein the determination unit includes a table walk circuit, which successively reads address range information on elements in the address range table and registers the read address range information in the address range register, and configured to execute the second determination on the basis of address range information registered in the address range register.

7. The arithmetic processing device according to claim 4, wherein

an address range table is reserved for each context and

when switching of the context is generated, the content of the address range register before the switching is saved in the memory and the content of the address range table after the switching is restored from the memory.

8. A control method of an information processing device comprising:

reserving a memory allocation area in a memory and registering address range information indicating an address range of the memory allocation area and management area identification information identifying a memory area allocation function in an address range table, in response to an execution of the memory area allocation function requesting memory area allocation;

referring to the address range table and performing determination processing as to whether or not an access destination address of a memory access instruction is within an address range indicated by the address range information that is registered in the address range table and that corresponds to the management area identification information of the memory access instruction, in response to an execution of the memory access instruction;

registering any management area identification information amongst a first management area identification information group, together with the address range information, in the address range table, in response to the execution of the memory area allocation function that requires an address range check, and configured to register second management area identification information that is distinguished from the first management area identification information group, together with the address range information, in the address range table, in response to the execution of the memory area allocation function that does not require the address range check; and

determining not that the access destination address is outside the address range, regardless of the determination as to whether or not the access destination address is within the address range indicating the address range information registered in the address range table, when the management area identification information held by the memory access instruction is the second management area identification information, in response to the execution of the memory access instruction.

9. A non-transitory computer readable storage medium storing a control program for an information processing device causing a computer to perform a process comprising:

reserving a memory allocation area in a memory and registering address range information indicating an address range of the memory allocation area and management area identification information identifying a memory area allocation function in an address range table, in response to an execution of the memory area allocation function requesting memory area allocation;

referring to the address range table and preforming determination processing as to whether or not an access destination address of a memory access instruction is within an address range indicated by the address range information that is registered in the address range table and that corresponds to the management area identification information of the memory access instruction, inresponse to an execution of the memory access instruction;

registering any management area identification information amongst a first management area identification information group, together with the address range information, in the address range table, in response to the execution of the memory area allocation function that requires an address range check, and configured to register second management area identification information that is distinguished from the first management area identification information group, together with the address range information, in the address range table, in response to the execution of the memory area allocation function that does not require the address range check; and

determining not that the access destination address is outside the address range, regardless of the determination as to whether or not the access destination address is within the address range indicating the address range information registered in the address range table, when the management area identification information held by the memory access instruction is the second management area identification information, in response to the execution of the memory access instruction.