Memory circuitry including computational circuitry for performing supplemental functions
First Claim
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1. A computer system comprising:
- primary processing circuitry;
a bus coupled to the primary processing circuitry; and
memory circuitry coupled to the bus, the memory circuitry physically separated from the primary processing circuitry, the memory circuitry configured as at least one integrated memory circuit including at least;
at least one layer of discrete storage cells configured to store and retrieve data and to provide to the bus, during accessing intervals, requested data for the primary processing circuitry, the at least one layer of discrete storage cells distributed over a substrate; and
computational circuitry distributed over the at least one layer of discrete storage cells distributed over the substrate, the computational circuitry configured for performing supplemental functions at least partially during one or more time periods that are not accessing intervals, the computational circuitry including at least logic distributed over the at least one layer of discrete storage cells configured for concurrently manipulating data in at least two portions of the logic distributed over the at least one layer of discrete storage cells, the concurrently manipulating data in at least two portions of the logic including at least two of;
a first portion of logic reading and decoding at least one address,a second portion of logic fetching data from the at least one address, anda third portion of logic performing at least one calculation on the fetched data.
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Abstract
A computer system includes but is not limited to a primary processing circuitry, a bus coupled to the primary processing circuitry, and memory circuitry coupled to the bus. The memory circuitry is physically separated from the primary processing circuitry. The memory circuitry includes at least one integrated memory circuit and computational circuitry. The at least one integrated memory circuit configured to store and retrieve data and to provide to the bus, during accessing intervals, requested data for the primary processing circuitry. The computational circuitry co-located with the at least one integrated memory circuit, the computational circuitry co-located with integrated memory circuit can be configured for performing supplemental functions at least partially during time periods that are not accessing intervals.
103 Citations
22 Claims
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1. A computer system comprising:
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primary processing circuitry; a bus coupled to the primary processing circuitry; and memory circuitry coupled to the bus, the memory circuitry physically separated from the primary processing circuitry, the memory circuitry configured as at least one integrated memory circuit including at least; at least one layer of discrete storage cells configured to store and retrieve data and to provide to the bus, during accessing intervals, requested data for the primary processing circuitry, the at least one layer of discrete storage cells distributed over a substrate; and computational circuitry distributed over the at least one layer of discrete storage cells distributed over the substrate, the computational circuitry configured for performing supplemental functions at least partially during one or more time periods that are not accessing intervals, the computational circuitry including at least logic distributed over the at least one layer of discrete storage cells configured for concurrently manipulating data in at least two portions of the logic distributed over the at least one layer of discrete storage cells, the concurrently manipulating data in at least two portions of the logic including at least two of; a first portion of logic reading and decoding at least one address, a second portion of logic fetching data from the at least one address, and a third portion of logic performing at least one calculation on the fetched data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A memory device operable to store data for primary processing circuitry via a bus, the memory device comprising:
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memory circuitry configured as at least one integrated memory circuit including at least; at least one layer of discrete storage cells configured to store and retrieve data and to provide to a bus, during accessing intervals, requested data for primary processing circuitry, the at least one layer of discrete storage cells distributed over a substrate; and computational circuitry distributed over the at least one layer of discrete storage cells distributed over the substrate, the computational circuitry configured for performing supplemental functions at least partially during one or more time periods that are not accessing intervals, the computational circuitry including at least logic distributed over the at least one layer of discrete storage cells configured for concurrently manipulating data in at least two portions of the logic distributed over the at least one layer of discrete storage cells, the concurrently manipulating data in at least two portions of the logic including at least two of; a first portion of logic reading and decoding at least one address, a second portion of logic fetching data from the at least one address, and a third portion of logic performing at least one calculation on the fetched data.
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Specification
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Current AssigneeElwha LLC (Intellectual Ventures LLC)
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Original AssigneeElwha LLC (Intellectual Ventures LLC)
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InventorsHyde, Roderick A., Pasch, Nicholas F., Tegreene, Clarence T.
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Primary Examiner(s)Alrobaye, Idriss N
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Assistant Examiner(s)Franklin, Richard B
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Application NumberUS13/841,042Publication NumberTime in Patent Office1,278 DaysField of SearchNoneUS Class Current1/1CPC Class CodesG06F 12/0831 using a bus scheme, e.g. wi...G06F 13/16 for access to memory bus G0...G11C 7/1006 Data managing, e.g. manipul...
