Transaction layer packet formatting

• US 9,442,855 B2
• Filed: 12/27/2014
• Issued: 09/13/2016
• Est. Priority Date: 11/02/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ajanovic, Jasmin, Wagh, Mahesh, Sethi, Prashant, Das Sharma, Debendra, Harriman, David J., Rosenbluth, Mark B., Bhatt, Ajay V., Barry, Peter, Rodgers, Scott Dion, Vasudevan, Anil, Muthrasanallur, Sridhar, Akiyama, James, Blankenship, Robert G., Falik, Ohad, Mendelson, Avi, Pardo, Ilan, Tamari, Eran, Weissmann, Eliezer, Shamia, Doron
• Primary Examiner(s): Alrobaye, Idriss N
• Assistant Examiner(s): Martinez, David E
• Application Number:
  US14/583,601
• Publication Number:
  US 20150161050A1
• Time in Patent Office: 626 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Claims

1. An apparatus comprising:

a receiver to receive a transaction layer packet from an input/output (I/O) device, wherein the I/O device comprises an add-in card, the transaction layer packet is to comprise a header, and the header is to comprise;

a first byte of the header,

a second byte adjacent to the first byte, wherein the second byte is to include a hint field, and the hint field is to identify a hint in the transaction layer packet; and

a no-snoop attribute to be included in another byte of the header subsequent to the first byte; and

protocol circuitry to process the transaction layer packet.

2. The apparatus of claim 1, wherein the protocol circuitry is to identify the hint from the hint field, and the apparatus further comprises coherency logic to determine whether to snoop a transaction based on the no-snoop attribute.

3. The apparatus of claim 2, wherein the coherency logic is to provide cache coherency management and cache coherency management is to include snoop requests of one or more shared memory locations.

4. The apparatus of claim 3, wherein cache coherency management is to further include filtering of the snoop requests.

5. The apparatus of claim 4, wherein the one or more shared memory locations include a first shared memory location and a second shared memory location, the transaction includes a request on the first shared memory location, the transaction layer packet is to include a cache coherency attribute, and the cache coherency attribute is to indicate that snoop requests corresponding to the request are to be filtered.

6. The apparatus of claim 5, wherein snoop requests of the second shared memory location are not filtered.

7. The apparatus of claim 5, wherein the cache coherency attribute is included in an attribute field of a transaction layer header of the packet.

8. The apparatus of claim 1, wherein the transaction layer packet is to correspond to a transaction.

9. The apparatus of claim 8, wherein the transaction is to comprise a request on shared memory.

10. The apparatus of claim 9, wherein the shared memory is to comprise a cache.

11. The apparatus of claim 10, wherein the shared memory is to comprise a system cache.

12. The apparatus of claim 10, wherein the shared memory is to comprise a local cache of a device.

13. The apparatus of claim 1, wherein the transaction is to comprise an atomic operation.

14. The apparatus of claim 1, wherein the receiver and protocol circuitry are included in a root controller of the apparatus.

15. An apparatus comprising:

a receiver to receive a transaction layer packet over a point-to-point interconnect, wherein the transaction layer packet is to correspond to a transaction and is to comprise a header, the header is to comprise a first byte of the header, a hint field is to be included in a second byte of the header adjacent to the first byte, and a transaction descriptor in another byte of the header subsequent to the second byte, the transaction descriptor is to comprise a no-snoop attribute, and the hint field is to identify a hint in the transaction layer packet;

a layered protocol stack to comprise a transaction layer, a link layer, and a physical layer, wherein the layered protocol stack is implemented at least in part by protocol circuitry to identify a hint from the hint field; and

coherency logic to identify, from the no-snoop attribute, whether snoop filtering applies to corresponding snoop requests of shared memory associated with the transaction.

16. An apparatus comprising:

an interface to;

interface with an add-in card; and

send a transaction layer packet to the add-in card, wherein the transaction layer packet is to correspond to a transaction and is to comprise a header, the header is to comprise;

a first byte of the header,

a second byte of the header adjacent to the first byte, wherein the second byte is to include a hint field, and the hint field is to identify a hint in the transaction layer packet, and

a transaction descriptor in another byte of the header subsequent to the second byte, wherein the transaction descriptor is to comprise a no-snoop attribute and the hint field is to identify a hint in the transaction layer packet.

17. An apparatus comprising:

protocol logic implemented at least in part in computing hardware, wherein the protocol logic is to;

receive a transaction layer packet from an input/output (I/O) device, the transaction layer packet is to comprise a header, and the header is to comprise;

a first byte of the header,

a second byte of the header adjacent to the first byte, wherein the second byte is to include a hint field to identify a hint in the transaction layer packet, and

a no-snoop attribute to be included in another byte of the header subsequent to the first byte; and

process the transaction layer packet based at least in part on the hint and the no-snoop attribute.

18. The apparatus of claim 17, wherein at least a portion of the protocol logic is implemented in software.

19. A method comprising:

receiving a transaction layer packet over a point-to-point interconnect, wherein the transaction layer packet is to correspond to a transaction and is to comprise a header, the header is to comprise a first byte of the header, a second byte of the header adjacent to the first byte, and a transaction descriptor in another byte of the header subsequent to the second byte, wherein the second byte is to include a hint field to identify a hint in the transaction layer packet, the transaction descriptor is to comprise a no-snoop attribute, and the hint field is to identify a hint in the transaction layer packet;

identifying a hint from the hint field; and

determining whether to snoop a transaction based on the no-snoop attribute.

20. The method of claim 19, further comprising filtering snoop requests based at least in part on the no-snoop attribute.

21. The method of claim 20, wherein the transaction comprises a request on shared memory.

22. A system:

a first device; and

a second device comprising I/O circuitry to;

receive a transaction layer packet from the first device over a point-to-point serial data link, wherein the transaction layer packet is to correspond to a transaction associated with shared memory;

identify a hint field in a header of the transaction layer packet, wherein the header is to comprise a first byte and a second byte of the header adjacent to the first byte, and the hint field is to be included in the second byte;

identify a no-snoop attribute in the header, wherein the no-snoop attribute is to be included in another byte of the header subsequent to the second byte.

23. The system of claim 22, wherein the second device comprises a root controller hub.

24. The system of claim 22, wherein the first device comprises an add-in card.

25. The system of claim 24, wherein the system comprises means to accept the add-in card.

26. An apparatus comprising:

a connector to accept a card device, wherein the connector comprises logic to;

receive a transaction layer packet from the card device, the transaction layer packet is to comprise a header, and the header is to comprise;

a first byte of the header,

a second byte adjacent to the first byte, wherein the second byte is to include a hint field, and the hint field is to identify a hint in the transaction layer packet; and

a no-snoop attribute to be included in another byte of the header subsequent to the first byte.

27. The apparatus of claim 26, wherein the connector is to be included in a server system.