Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device

• US 9,443,054 B1
• Filed: 04/19/2014
• Issued: 09/13/2016
• Est. Priority Date: 05/29/2003
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Betz, Vaughn, Pantofaru, Caroline, Swartz, Jordan
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US14/256,949
• Time in Patent Office: 878 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method for designing a system on a programmable logic device (PLD) is disclosed. Routing resources are selected for a user specified signal on the PLD in response to user specified routing constraints. Routing resources are selected for a non-user specified signal on the PLD without utilizing the user specified routing constraints.

Claims

1. A method for designing a system on a target device, comprising:

selecting routing resources for a user specified segment on a target device in response to user specified routing constraints specifying one of a specific wire and a category of wires on the target device; and

selecting routing resources for a non-user specified segment on the target device without utilizing the user specified routing constraints, wherein at least one of the selecting is performed by a processor.

2. The method of claim 1, further comprising generating a routing constraints file that includes user specified routing constraints for routing a system on the target device.

3. The method of claim 1, wherein selecting routing resources for the user specified segments comprises ordering segments such that segments having user-specified routing constraints are routed before segments not having user-specified routing constraints.

4. The method of claim 1, further comprising identifying erroneous user-specified routing constraints.

5. The method of claim 4, further comprising discarding identified erroneous user-specified routing constraints from consideration prior to selecting routing resources.

6. The method of claim 1, wherein the category of wires describe an orientation of wires.

7. The method of claim 1, wherein the category of wires describe a length of wires.

8. The method of claim 1, wherein the target device is a field programmable gate array (FPGA).

9. A system designer, comprising:

a routing unit that selects routing resources for a user specified segment on a target device in response to user specified routing constraints specifying one of a specific wire and a category of wires on the target device, and that selects routing resources for a non-user specified segment on the target device without utilizing the user specified routing constraints.

10. The system designer of claim 9, further comprising a system designer interface unit that generates a routing constraints file that includes user specified routing constraints for routing a system on the target device.

11. The system designer of claim 9, wherein the routing unit comprises an ordering unit that orders segments such that segments having user specified routing constraints are routed before segments not having user specified routing constraints.

12. The system designer unit of claim 9, wherein the routing unit comprises a parsing unit that identifies erroneous user specified routing constraints.

13. The system designer of claim 12, wherein the parsing unit discards the identified erroneous user specified routing constraints from consideration prior to selecting routing resources.

14. The system designer of claim 9, wherein the category of wires describe an orientation of wires.

15. The system designer of claim 9, wherein the category of wires describe a length of wires.

16. A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method comprising:

selecting routing resources for a user specified segment on a target device in response to user specified routing constraints specifying one of a specific wire and a category of wires on the target device;

selecting routing resources for a non-user specified segment on the target device without utilizing the user specified routing constraints; and

ordering segments such that segments having user specified routing constraints are routed before segments not having routing constraints.

17. The non-transitory computer readable medium of claim 16, wherein the method further comprises generating a routing constraints file that includes user specified routing constraints for routing a system on the target device.

18. The non-transitory computer readable medium of claim 16, wherein selecting routing resources for the user specified segments comprises ordering segments such that segments having user-specified routing constraints are routed before segments not having user-specified routing constraints.

19. The non-transitory computer readable medium of claim 16, wherein the method further comprises identifying erroneous user-specified routing constraints.

20. The non-transitory computer readable medium of claim 19, further comprising discarding identified erroneous user-specified routing constraints from consideration prior to selecting routing resources.