VSL-based VT-compensation and analog program scheme for NAND array without CSL
First Claim
1. A NAND memory array with BL-hierarchical structure for concurrent All-BL (ABL), All-Vtn-Program (AnP) and Alternate-WL (Alt-WL) program, Half-BL (HBL) Odd/Even program-verify and read operations, the NAND memory array comprising:
- a NAND plane comprising N number of columns of NAND memory cells connected in series along a bitline (BL) direction, the N number of columns being cascaded one another along a wordline (WL) direction perpendicular to the BL-direction, the NAND plane being divided to J number of HG groups arranged in the BL-direction, each HG group including L number of MG groups, each MG group including J′
number of LG groups, each LG group including H number of blocks, each block including N number of strings, each string including K number of NAND memory cells and a pair of string-select transistors respectively located in two ends of the string and a pair of dummy memory cells, wherein N, J, L, J′
, H, and K are respectively selected from integers of 2 and greater based on memory chip design;
a two-level bit line hierarchical structure comprising J rows of N number of first broken metal lines laid at a first level along the BL-direction connected by J−
1 rows of N number of GBL-divide transistors as N global bit lines (GBLs) through the J HG groups for connecting N corresponding columns to a page buffer, and N number of second broken metal lines per each MG group laid at a second level below the first level along the BL-direction with all Even-numbered N/2 second broken metal lines being independently grounded and N number of third broken metal lines per each same MG group laid at a third level below the second level along the BL-direction with all Odd-numbered N/2 third broken metal lines being independently grounded and all N/2 Odd-numbered second broken metal lines and all N/2 Even-numbered third broken metal lines together forming N local bit lines (LBLs) respectively connected to N GBLs via N Y-pass devices, each of the N LBLs being divided to J′
broken-LBLs by J′
-1 rows of N number of LBL-divide transistors, each broken-LBL being associated with a LG group and configured to connect either a drain node of an Odd-numbered string as a local bit line or a source node of a neighboring Even-numbered string as a local source line in alternative manner through the H number of strings along the BL-direction in the LG group without a common source line laid in the WL-direction in each block for all N number of strings, each LBL forming an on-chip capacitor CMG with full electrical shielding at each of the second and third level;
a row of N/2 number of Odd precharge transistors per each LG group having corresponding drain nodes coupled to respective N/2 Odd-numbered broken-LBLs and corresponding source nodes coupled to a common precharge power line laid at a fourth level below the third level along the WL-direction, and a row of N/2 number of Even precharge transistors per same LG group having corresponding drain nodes coupled to respective Even-numbered broken-LBLs and corresponding source nodes coupled to the common precharge power line, the common precharge power line being optionally connected to a medium-high voltage up to 7V or connected to ground or other voltages for discharging;
wherein each row of N memory cells in any block forms a page and multiple pages in one or more selected LG groups are configured to perform multi-page concurrent All-BL (ABL), All-threshold-states-program (AnP), and Alternate-WL (Alt-WL) program operation with individual LBL program-voltage compensations in several program passes and to perform multi-page concurrent HBL Odd/Even program-verify and read operations in two cycles with option of applying individual source-line-voltage-based transistor threshold-level compensations for substantially reducing WL-WL and BL-BL coupling effects.
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Abstract
A YUKAI NAND array comprising multiple strings of all TLC and mixed TLC+SLC memory cells associated with hierarchical global/local bit lines (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line (LSL) with full BL-shielding without wasting extra silicon area and without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding to perform concurrent ABL, AnP and Alt-WL program under multi-passes program schemes with LBL program voltage compensations and half-BL Odd/Even program-verify and read operations with individual VSL-based Vt-compensation to mitigate high WL-WL and BL-BL coupling effects.
11 Citations
57 Claims
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1. A NAND memory array with BL-hierarchical structure for concurrent All-BL (ABL), All-Vtn-Program (AnP) and Alternate-WL (Alt-WL) program, Half-BL (HBL) Odd/Even program-verify and read operations, the NAND memory array comprising:
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a NAND plane comprising N number of columns of NAND memory cells connected in series along a bitline (BL) direction, the N number of columns being cascaded one another along a wordline (WL) direction perpendicular to the BL-direction, the NAND plane being divided to J number of HG groups arranged in the BL-direction, each HG group including L number of MG groups, each MG group including J′
number of LG groups, each LG group including H number of blocks, each block including N number of strings, each string including K number of NAND memory cells and a pair of string-select transistors respectively located in two ends of the string and a pair of dummy memory cells, wherein N, J, L, J′
, H, and K are respectively selected from integers of 2 and greater based on memory chip design;a two-level bit line hierarchical structure comprising J rows of N number of first broken metal lines laid at a first level along the BL-direction connected by J−
1 rows of N number of GBL-divide transistors as N global bit lines (GBLs) through the J HG groups for connecting N corresponding columns to a page buffer, and N number of second broken metal lines per each MG group laid at a second level below the first level along the BL-direction with all Even-numbered N/2 second broken metal lines being independently grounded and N number of third broken metal lines per each same MG group laid at a third level below the second level along the BL-direction with all Odd-numbered N/2 third broken metal lines being independently grounded and all N/2 Odd-numbered second broken metal lines and all N/2 Even-numbered third broken metal lines together forming N local bit lines (LBLs) respectively connected to N GBLs via N Y-pass devices, each of the N LBLs being divided to J′
broken-LBLs by J′
-1 rows of N number of LBL-divide transistors, each broken-LBL being associated with a LG group and configured to connect either a drain node of an Odd-numbered string as a local bit line or a source node of a neighboring Even-numbered string as a local source line in alternative manner through the H number of strings along the BL-direction in the LG group without a common source line laid in the WL-direction in each block for all N number of strings, each LBL forming an on-chip capacitor CMG with full electrical shielding at each of the second and third level;a row of N/2 number of Odd precharge transistors per each LG group having corresponding drain nodes coupled to respective N/2 Odd-numbered broken-LBLs and corresponding source nodes coupled to a common precharge power line laid at a fourth level below the third level along the WL-direction, and a row of N/2 number of Even precharge transistors per same LG group having corresponding drain nodes coupled to respective Even-numbered broken-LBLs and corresponding source nodes coupled to the common precharge power line, the common precharge power line being optionally connected to a medium-high voltage up to 7V or connected to ground or other voltages for discharging; wherein each row of N memory cells in any block forms a page and multiple pages in one or more selected LG groups are configured to perform multi-page concurrent All-BL (ABL), All-threshold-states-program (AnP), and Alternate-WL (Alt-WL) program operation with individual LBL program-voltage compensations in several program passes and to perform multi-page concurrent HBL Odd/Even program-verify and read operations in two cycles with option of applying individual source-line-voltage-based transistor threshold-level compensations for substantially reducing WL-WL and BL-BL coupling effects. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57)
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Specification