Determination of bit line to low voltage signal shorts

• US 9,443,612 B2
• Filed: 07/10/2014
• Issued: 09/13/2016
• Est. Priority Date: 07/10/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Sbade, Jagdish M., Magia, Sagar
• Primary Examiner(s): Yang, Han
• Assistant Examiner(s): Chen, Xiaochun L
• Application Number:
  US14/328,037
• Publication Number:
  US 20160012915A1
• Time in Patent Office: 796 Days
• Field of Search: 365/185.11
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/06 Acceleration testing
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

Abstract

A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.

Claims

1. A method of determining defects in a non-volatile memory circuit, the method comprising:

performing a stress operation on the non-volatile memory circuit having a plurality of memory cells, where each of the memory cells is connectable by one of a plurality of bit lines to one of a plurality of sense amplifiers, and where each of the bit lines is connectable to an associated one of the sense amplifiers by a corresponding switch, the stress operation including;

for a first set of one or more bit lines and a second set of one or more bit lines, while the switches corresponding to the first and second sets of bit lines are off, concurrently;

applying a high voltage level to the first set of bit lines; and

setting the sense amplifiers associated with the second set of bit lines to a sense amplifier operating level,

wherein at least one bit line of the first set of bit lines is adjacent to at least one of the sense amplifiers associated with the second set of bit lines; and

subsequently performing a defect determination operation, including;

with the corresponding switches for the first and second sets of bit lines off and the sense amplifiers associated with the second set of bit lines set to the sense amplifier operating level, supplying the first set of bit lines from a high voltage supply; and

determining whether the high voltage supply can maintain the first set of bit lines at a first voltage level.

2. The method of claim 1, wherein the first voltage level is the high voltage level.

3. The method of claim 2, wherein the high voltage level is an erase voltage level.

4. The method of claim 3, wherein the high voltage supply is a charge pump that supplies the high voltage level, wherein when determining whether the high voltage supply can maintain the first set of bit lines at the high voltage level the charge pump is operated at a lower drive level than when the high voltage level is used in performing an erase operation.

5. The method of claim 4, wherein the charge pump is operated at the lower drive level by using a lower pump clock frequency.

6. The method of claim 1, wherein the sense amplifier operating level is ground.

7. The method of claim 1, wherein the sense amplifier operating level is a high logic level.

8. The method of claim 1, wherein the sense amplifier operating level is a bit line pre-charge level.

9. The method of claim 1, wherein the bit lines of the second set of bit lines are the same bit lines as the bit lines of the first set of bit lines.

10. The method of claim 9, wherein the non-volatile memory circuit further comprises a plurality of blocks and the first set of bit lines corresponds to bit lines spanning a set of one or more memory blocks.

11. The method of claim 10, further comprising:

in response to determining that the high voltage supply cannot maintain the first set of bit lines at the first voltage, marking a corresponding set of memory blocks as defective.

12. The method of claim 11, wherein the set of memory blocks corresponds to a plane.

13. The method of claim 10, wherein the set of memory blocks corresponds to a die.

14. The method of claim 10, wherein the non-volatile memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

15. The method of claim 14, wherein the plurality of blocks are formed of a plurality of NAND strings, each having multiple memory cells connected in series between one or more source select gates and one or more drain select gates, the memory cells being connected along word lines and the source and drain select gates being respectively connected along source and drain select lines, the NAND strings being formed above a P well and each connected, through the corresponding drain select gates, to the associated bit line, and

wherein the NAND strings run in a vertical direction relative to the substrate, and the word lines, source and drain select lines, and bit lines run in a horizontal direction relative to the silicon substrate.

16. The method of claim 15, wherein applying the high voltage level to the first set of bit lines comprises:

applying the high voltage level to the P well below one or more first blocks while allowing the word lines, source and drain select lines, and bit lines of the NAND strings corresponding to said first blocks to float.

17. The method of claim 16, wherein the first blocks are all of the blocks formed over the P well.

18. The method of claim 16, wherein supplying the first set of bit lines from the high voltage supply comprises:

supplying the P well below one or more of the first blocks from the high voltage supply allowing the word lines, source and drain select lines, and bit lines of the NAND strings corresponding to said first blocks to float.

19. The method of claim 1, wherein supplying the first set of bit lines from the high voltage supply includes:

applying a continuous high voltage.

20. The method of claim 19, wherein a duration for which the continuous high voltage is applied is settable.

21. The method of claim 1, wherein supplying the first set of bit lines from the high voltage supply includes:

applying a series of high voltage pulses.

22. The method of claim 21, wherein a duration of the pulses is settable.

23. The method of claim 21, wherein a number of the pulses is settable.