Bad memory unit detection in a solid state drive

• US 9,443,616 B2
• Filed: 04/28/2014
• Issued: 09/13/2016
• Est. Priority Date: 04/02/2014
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Chen, Zhengang, Cohen, Earl T., Haratsch, Erich F., Werner, Jeremy
• Primary Examiner(s): Britt, Cynthia
• Assistant Examiner(s): Hossain, Sazzad
• Application Number:
  US14/263,189
• Publication Number:
  US 20150287478A1
• Time in Patent Office: 869 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/07 Responding to the occurrence of a fault, e.g. fault tolerance
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0403 during or with feedback to manufacture
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/765 in solid state disks

Abstract

An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory unit granularities each having a size less than a total size of the memory. The controller is configured to process a plurality of I/O requests to the memory units of the memory that are not marked as bad on a memory unit list. The controller is configured to track a plurality of bad blocks of the memory. The controller is configured to determine which of the memory units to mark as bad based on a test of whether a unit of memory larger than a block of the memory has failed. The test is based on a threshold of the bad blocks in the unit of memory.

Claims

1. An apparatus comprising:

a memory configured to store data, the memory comprising a plurality of dies each (i) having a size less than a total size of the memory and (ii) comprising a plurality of planes, each of the planes comprising a plurality of blocks; and

a controller configured to (i) process a plurality of input/output requests to/from the memory, (ii) determine which of the blocks are bad in each of the dies and planes, and (iii) determine whether to mark one or more of the dies as bad in response to a first test and whether to mark one or more planes within one of the dies as bad in response to a second test, wherein (a) the first test is configured to analyze the bad blocks in each of the dies, (b) if one of the dies fails the first test, the controller is configured to perform the second test on each of the planes of the die that failed the first test, (c) the second test is configured to analyze the bad blocks in each of the planes of the die that failed the first test, (d) the first test is based on determining whether a number of bad blocks in one of the dies exceeds a threshold number of bad blocks, (e) the second test is based on determining whether a number of bad blocks in one of the planes exceeds a threshold number of bad blocks and (f) the dies that fail the first test are not marked as bad if one or more planes in the dies that fail the first test do not fail the second test.

2. The apparatus according to claim 1, wherein each of the plurality of dies and the plurality of planes are memory units of the memory.

3. The apparatus according to claim 2, wherein the first test and the second test are performed (A) during a lifetime of the apparatus in a first mode, and (B) during a manufacturer self-test in a second mode.

4. The apparatus according to claim 3, wherein the first test and the second test performed during the lifetime of the apparatus are performed on demand.

5. The apparatus according to claim 3, wherein the threshold number of bad blocks of the first test and the second test performed during the lifetime of the apparatus is compared to a consecutive number of the bad blocks in the memory unit.

6. The apparatus according to claim 3, wherein the first test and the second test performed during the manufacturer self-test are embedded in procedures of the manufacturer self-test.

7. The apparatus according to claim 3, wherein the threshold number of bad blocks of the first test and the second test performed during the manufacturer self-test is compared to a total number of the bad blocks in the memory unit.

8. The apparatus according to claim 2, wherein the threshold number of bad blocks of the first test and the second test is compared to a number of the blocks in the memory unit having program/erase errors in a first mode and read errors in a second mode.

9. The apparatus according to claim 1, wherein the first test and the second test track errors in the blocks of the memory.

10. The apparatus according to claim 9, wherein the tracked errors are program/erase errors in a first mode and read errors in a second mode.

11. The apparatus according to claim 10, wherein the program/erase errors are tracked separately from the read errors.

12. The apparatus according to claim 2, wherein the controller is further configured to pro-actively respond to the memory units marked as bad.

13. The apparatus according to claim 1, wherein the threshold number of bad blocks of the first test and the second test is adjustable.

14. The apparatus according to claim 1, wherein the controller is further configured to implement an error recovery correction capability for a memory page and a memory block.

15. The apparatus according to claim 2, wherein the first test and the second test check a number of iterations to converge and a number of bit errors of the blocks of the memory unit.

16. The apparatus according to claim 2, wherein the first test and the second test check if communication can be established with the memory unit.

17. The apparatus according to claim 1, wherein the memory and the controller form a solid-state drive.

18. The apparatus according to claim 2, wherein controller is further configured to (a) retire the memory units marked as bad and (b) avoid bad block handling for the blocks in the memory units marked as bad.

19. An apparatus comprising:

an interface configured to process a plurality of read/write operations to/from a memory, the memory comprising a plurality of dies each (i) having a size less than a total size of the memory and (ii) comprising a plurality of planes, each of the planes comprising a plurality of blocks; and

a control circuit configured to (i) determine which of the blocks are bad in each of the dies and planes, and (ii) determine whether to mark one or more of the dies as bad in response to a first test and whether to mark one or more planes within one of the dies as bad in response to a second test wherein (a) the first test is configured to analyze the bad blocks in each of the dies, (b) if one of the dies fails the first test, the control circuit is configured to perform the second test on each of the planes of the die that failed the first test, (c) the second test is configured to analyze the bad blocks in each of the planes of the die that failed the first test, (d) the first test is based on determining whether a number of bad blocks in the dies exceeds a threshold number of the bad blocks, (e) the second test is based on determining whether a number of bad blocks in one of the planes exceeds a threshold number of bad blocks and (f) the dies that fail the first test are not marked as bad if one or more planes in the dies that fail the first test do not fail the second test.

20. A method for detecting bad dies and planes in a solid-state drive (SSD), comprising the steps of:

processing a plurality of read/write operations to/from a memory, the memory comprising a plurality of dies and planes each (i) having a size less than a total size of the memory and (ii) comprising a plurality of planes, each of the planes comprising a plurality of blocks;

determining which of the blocks are bad in each of the dies and planes; and

determining whether to mark one or more of the dies as bad in response to a first test and whether to mark one or more planes within one of the dies as bad in response to a second test, wherein (a) the first test is configured to analyze the bad blocks in each of the dies, (b) the second test is performed on each of the planes of the die that failed the first test, if one of the dies fails the first test, (c) the second test is configured to analyze the bad blocks in each of the planes of the die that failed the first test, (d) the first test is based on determining whether a number of bad blocks in the dies exceeds a threshold number of the bad blocks, (e) the second test is based on determining whether a number of bad blocks in one of the planes exceeds a threshold number of bad blocks and (f) the dies that fail the first test are not marked as bad if one or more planes in the dies that fail the first test do not fail the second test.