3DIC stacking device and method of manufacture

• US 9,443,783 B2
• Filed: 09/14/2012
• Issued: 09/13/2016
• Est. Priority Date: 06/27/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Jing-Cheng, Yu, Chen-Hua
• Primary Examiner(s): Ingham, John C
• Assistant Examiner(s): MUSE, ISMAIL A
• Application Number:
  US13/619,877
• Publication Number:
  US 20140001645A1
• Time in Patent Office: 1,460 Days
• Field of Search: 257/686, 257/700, 257/777, 438/109, 438/464
• US Class Current: 1/1
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/1145 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11462 : Electroplating
• CPC Class Codes: H01L 2224/11849 : Reflowing
• CPC Class Codes: H01L 2224/12105 : Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13023 : the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13024 : the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/14134 : covering only portions of the surface to be connected
• CPC Class Codes: H01L 2224/14144 : covering only portions of the surface to be connected
• CPC Class Codes: H01L 2224/14154 : covering only portions of the surface to be connected
• CPC Class Codes: H01L 2224/14164 : covering only portions of the surface to be connected
• CPC Class Codes: H01L 2224/14181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/17181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/81895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/83104 : by applying pressure, e.g. by injection
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/3171 : the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position.

Claims

1. A method for forming a device comprising:

placing two or more bottom dies on a first carrier wafer;

forming a first molding compound between the two or more bottom dies such that electrical contacts on the two or more bottom dies are exposed, wherein the exposed electrical contacts are located on a side of the two or more bottom dies that faces away from the first carrier wafer, wherein the exposed electrical contacts on the two or more bottom dies are exposed using at least in part a grinding process;

attaching the two or more bottom dies and the first molding compound to a second carrier wafer with an adhesive, wherein the adhesive is in physical contact with the electrical contacts;

thinning the two or more bottom dies to expose through vias formed through the two or more bottom dies, wherein the thinning the two or more bottom dies is performed on an opposite side of the two or more bottom dies than the exposed electrical contacts side;

forming electrical contacts to the through vias along a backside of the two or more bottom dies; and

attaching one or more top dies to the one or more bottom dies.

2. The method of claim 1, wherein the first molding compound covers a bottom side of the two or more bottom dies.

3. The method of claim 1, wherein the forming a first molding compound comprises thinning the first molding compound to expose the electrical contacts on the two or more bottom dies.

4. The method of claim 1, further comprising forming a redistribution layer formed over the two or more bottom dies.

5. The method of claim 4, wherein the redistribution layer extends over the first molding compound.

6. The method of claim 1, further comprising a second molding compound formed over the one or more top dies.

7. A method of manufacturing a semiconductor device, the method comprising:

attaching a first semiconductor die to a carrier, the first semiconductor die comprising first external contacts, wherein a surface of the first external contacts facing away from the carrier is covered by a polymer material;

attaching a second semiconductor die to the carrier, the second semiconductor die comprising second external contacts;

encapsulating the first semiconductor die and the second semiconductor die with an encapsulant different from the polymer material, wherein the encapsulant is a single material;

removing a portion of the encapsulant to expose a first surface of the first external contacts and a second surface of the second external contacts, wherein the first surface and the second surface face away from the carrier;

attaching the first external contacts to a second carrier with an adhesive, the adhesive being in physical contact with the first external contacts;

thinning the first semiconductor die and the second semiconductor die to remove first semiconductor material from over a first conductive material to expose first through substrate vias in the first semiconductor die and to remove second semiconductor material from over a second conductive material to expose second through substrate vias in the second semiconductor die, wherein the first semiconductor material is on an opposite side of the first semiconductor die than the first surface; and

electrically connecting a third semiconductor die to the first through substrate vias and electrically connecting a fourth semiconductor die to the second through substrate vias, wherein the third semiconductor die has a first width of between about 1 mm and about 20 mm, the first semiconductor die has a second width of between about 3 mm and about 14 mm, and wherein the second width is less than the first width.

8. The method of claim 7, further comprising encapsulating the third semiconductor die and the fourth semiconductor die.

9. The method of claim 7, further comprising forming a third external contact on the first external contacts after the encapsulating the first semiconductor die and the second semiconductor die.

10. The method of claim 7, further comprising forming a redistribution layer in electrical connection with the first external contacts.

11. The method of claim 10, wherein the forming the redistribution layer occurs prior to the thinning the first semiconductor die and the second semiconductor die.

12. The method of claim 10, further comprising forming third external contacts in electrical connection with the redistribution layer after the electrically connecting the third semiconductor die to the first through substrate vias.

13. The method of claim 7, wherein the electrically connecting the third semiconductor die to the first through substrate vias further comprises offsetting the third semiconductor die from the first semiconductor die.

14. The method of claim 7, wherein the third semiconductor die overhangs the first semiconductor die after the electrically connecting the third semiconductor die to the first through substrate vias.

20. The method of claim 7, further comprising attaching conductive bumps to the first external contacts.

15. A method of manufacturing a semiconductor device, the method comprising:

attaching a first semiconductor die to a carrier wafer, the first semiconductor die comprising first electrical contacts facing away from the carrier wafer and a first surface facing towards the carrier wafer;

attaching a second semiconductor die to the carrier wafer, the second semiconductor die comprising second electrical contacts facing away from the carrier wafer and a second surface facing towards the carrier wafer;

encapsulating the first semiconductor die and the second semiconductor die with molding compound, wherein a first portion of the molding compound is over and in direct physical contact with the first semiconductor die and a second portion of the molding compound is over and in direct physical contact with the second semiconductor die;

grinding the first portion of the molding compound and the second portion of the molding compound over the first semiconductor die and the second semiconductor die until the first electrical contacts and the second electrical contacts have been exposed by the grinding;

applying an adhesive to be in physical contact with the first electrical contacts and the second electrical contacts and adhering the first electrical contacts and the second electrical contacts to a second carrier wafer with the adhesive;

subsequent to the grinding the first portion of the molding compound and the second portion of the molding compound, removing a portion of the first surface over first vias and removing a portion of the second surface over second vias to thin the first semiconductor die and the second semiconductor die and expose first through vias and second through vias, wherein the first vias were covered by the first surface prior to the removing the portion of the first surface;

forming a first redistribution layer in electrical connection with the first through vias;

attaching a third semiconductor die to the first redistribution layer;

attaching a fourth semiconductor die to the first redistribution layer;

encapsulating the third semiconductor die and the fourth semiconductor die with an encapsulant, wherein the first redistribution layer is located between the encapsulant and the molding compound in a direction perpendicular with a major surface of the first semiconductor device; and

grinding the encapsulant to expose the third semiconductor die and the fourth semiconductor die.

16. The method of claim 15, further comprising forming a second redistribution layer in electrical connection with the first electrical contacts.

17. The method of claim 16, wherein the forming the second redistribution layer occurs prior to the removing the portion of the first surface and the second surface.

18. The method of claim 15, wherein the attaching the third semiconductor die further comprises offsetting the third semiconductor die from the first semiconductor die.

19. The method of claim 15, wherein the third semiconductor die overhangs the first semiconductor die after the attaching the third semiconductor die to the first semiconductor die by a distance of between about 100 μ

m and about 3 mm.