Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation

• US 9,443,828 B2
• Filed: 04/23/2015
• Issued: 09/13/2016
• Est. Priority Date: 07/22/2009
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Inventors: Pagaila, Reza A., Do, Byung Tai, Chua, Linda Pei Ee
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US14/694,811
• Publication Number:
  US 20150228628A1
• Time in Patent Office: 509 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer.

Claims

1. A semiconductor device, comprising:

a first semiconductor die;

a first thermally conductive layer formed over the first semiconductor die;

an interconnect structure formed over the first semiconductor die; and

a first conductive via formed through the first semiconductor die.

2. The semiconductor device of claim 1, further including an encapsulant deposited around the first semiconductor die.

3. The semiconductor device of claim 2, further including a second conductive via formed through the encapsulant.

4. The semiconductor device of claim 1, further including a second thermally conductive layer formed over the first semiconductor die opposite the first thermally conductive layer.

5. The semiconductor device of claim 1, further including a second semiconductor die disposed over the first thermally conductive layer opposite the first semiconductor die.

6. The semiconductor device of claim 1, further including a heat sink disposed over the first semiconductor die.

7. A semiconductor device, comprising:

a first semiconductor die;

a first thermally conductive layer formed over the first semiconductor die; and

a first conductive via formed through the first semiconductor die.

8. The semiconductor device of claim 7, further including an encapsulant deposited around the first semiconductor die.

9. The semiconductor device of claim 8, further including a second conductive via formed through the encapsulant.

10. The semiconductor device of claim 7, further including a second thermally conductive layer formed over the first semiconductor die opposite the first thermally conductive layer.

11. The semiconductor device of claim 7, further including an interconnect structure formed over the first semiconductor die opposite the first thermally conductive layer.

12. The semiconductor device of claim 7, further including a second semiconductor die disposed over the first thermally conductive layer opposite the first semiconductor die.

13. The semiconductor device of claim 7, further including a heat sink disposed over the first semiconductor die.

14. A semiconductor device, comprising:

a first semiconductor die;

a first thermally conductive layer formed over the first semiconductor die; and

an encapsulant deposited over the first semiconductor die and first thermally conductive layer.

15. The semiconductor device of claim 14, further including an interconnect structure formed over the first semiconductor die opposite the first thermally conductive layer.

16. The semiconductor device of claim 14, further including a conductive via formed through the first semiconductor die.

17. The semiconductor device of claim 14, further including an interconnect structure formed over the first thermally conductive layer.

18. The semiconductor device of claim 14, further including a second semiconductor die disposed over the first thermally conductive layer opposite the first semiconductor die.

19. The semiconductor device of claim 14, further including a heat sink disposed over the first semiconductor die.

20. A semiconductor device, comprising:

a first semiconductor die; and

a first thermally conductive layer formed over the first semiconductor die within a footprint of the first semiconductor die.

21. The semiconductor device of claim 20, further including an encapsulant deposited around the first semiconductor die.

22. The semiconductor device of claim 21, further including a conductive via formed through the encapsulant.

23. The semiconductor device of claim 20, further including an interconnect structure formed over the first semiconductor die.

24. The semiconductor device of claim 20, further including a conductive via formed through the first semiconductor die.

25. The semiconductor device of claim 20, further including a second semiconductor die disposed over the first semiconductor die opposite the first thermally conductive layer.