Methods for performing embedded wafer-level packaging (eWLP) and eWLP devices, packages and assemblies made by the methods

• US 9,443,835 B2
• Filed: 07/14/2014
• Issued: 09/13/2016
• Est. Priority Date: 03/14/2014
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Krabe, Detlef Bernd, Weigert, Martin
• Primary Examiner(s): NIKMANESH, SEAHVOSH J
• Application Number:
  US14/330,022
• Publication Number:
  US 20150262984A1
• Time in Patent Office: 792 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/2518 being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/167 : comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 31/02002 : Arrangements for conducting electric current to or from the device in operations
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 31/12 : structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto semiconductor devices with at least one potential barrier or surface barrier adapted for light emission H01L33/00; amplifiers using electroluminescent element and photocell H03F17/00; electroluminescent light sources per se H05B33/00
• CPC Class Codes: H01L 31/167 : the light sources and the devices sensitive to radiation all being semiconductor devices characterised by potential barriers

Abstract

Embedded Wafer-Level Packaging (eWLP) methods and optoelectronic devices, packages and assemblies made by the eWLP methods are described. The eWLP methods allow electrical interconnections to be easily and economically made to the back sides of the chips of the eWLP wafer using eWLP wafer-level processes, thereby eliminating the need to use TMVs or TSVs to make such interconnections. The eWLP methods also allow thermal and optical interconnections between the back side and the front side of the eWLP wafer to be easily and economically made. In addition, the eWLP methods allow electrical and optical interfaces to be formed on the front side and/or on the back side of the eWLP wafer. The eWLP methods may be used to form a variety of very thin optoelectronic devices, packages and assemblies having a various useful configurations with high volume, yield and throughput.

Claims

1. An embedded Wafer-Level Packaging (eWLP) method comprising:

forming an eWLP artificial wafer comprising a plurality of components partially encapsulated within a hard molded compound, wherein front sides of the components are outside of the hard molded compound and disposed on a front side of the eWLP artificial wafer, the components including an integrated circuit (IC) chip of a first type, the IC chip of the first type having at least a first electrical contact element disposed on the front side thereof and at least a second electrical contact element disposed on a back side thereof, the second electrical contact element being electrically coupled with a first electrically-conductive back side interconnect element, a portion of the interconnect element being outside of the hard molded compound and disposed on a back side of the eWLP artificial wafer;

forming an electrical interface on either the front side or the back side of the eWLP artificial wafer; and

dicing the eWLP wafer into a plurality of eWLP packages, each eWLP package including at least one of the IC chips of the first type.

2. The eWLP method of claim 1, wherein the back side interconnect element comprises a semiconductor material that has been doped to increase an electrical conductivity of the semiconductor material.

3. The eWLP method of claim 2, wherein the semiconductor material is n-doped semiconductor material.

4. The eWLP method of claim 3, wherein the semiconductor material is n-doped silicon.

5. The eWLP method of claim 1, wherein the components further include an IC chip of a second type that is different from the first type, the IC chip of the second type having at least a first electrical contact element disposed on the front side thereof, and wherein each eWLP package includes at least one of the IC chips of the second type.

6. The eWLP method of claim 5, wherein a back side of each IC chip of the second type is outside of the hard molded compound and is disposed on the back side of the eWLP artificial wafer, and wherein a bulk material of the IC chip of the second type provides an electrically-conductive pathway between the front side of the eWLP wafer and the back side of the eWLP wafer.

7. The eWLP method of claim 6, wherein the back side of each IC chip of the second type has at least a second electrical contact element thereon, and wherein one or more p-type or n-type wells formed in the bulk material electrically isolate the first electrical contact element disposed on the front side of the IC chip of the second type from the second electrical contact element disposed on the back side of the IC chip of the second type.

8. The eWLP method of claim 5, wherein a back side of the IC chip of the second type has a second electrical contact element thereon, the second electrical contact element disposed on the back side of the IC chip of the second type being electrically coupled with a second electrically-conductive back side interconnect element, a portion of the second interconnect element being outside of the hard molded compound and disposed on the back side of the eWLP artificial wafer.

9. The eWLP method of claim 1, wherein the components further include a block of bulk material having a front side that is outside of the hard molded compound and is disposed on the front side of the eWLP artificial wafer and having a back side that is outside of the hard molded compound and is disposed on the back side of the eWLP artificial wafer, and wherein the bulk material provides an electrically-conductive pathway between the front side of the eWLP wafer and the back side of the eWLP wafer, and wherein each eWLP package includes at least one of the blocks of bulk material.

10. The eWLP method of claim 1, wherein the components further include an IC chip of a second type that is different from the first type, the IC chip of the second type having one or more vias formed therein that extend from a front side of the chip of the second type to a back side of the chip of the second type, and wherein each eWLP package includes at least one of the IC chips of the second type.

11. The eWLP method of claim 10, wherein the vias comprise electrically-conductive material and wherein a bulk material of the IC chip of the second type electrically isolates the vias from one another.

12. The eWLP method of claim 10, wherein the vias comprise thermally-conductive material and wherein a bulk material of the IC chip of the second type thermally isolates the vias from one another.

13. The eWLP method of claim 10, wherein the vias comprise material that is transparent to at least one wavelength of light, and wherein a bulk material of the IC chip of the second type is opaque to said at least one wavelength of light.

14. An embedded Wafer-Level Packaging (eWLP) assembly comprising:

an eWLP package diced from an eWLP artificial wafer, the eWLP package comprising at least an integrated circuit (IC) chip of a first type partially encapsulated within a hard molded compound of the eWLP package, the IC chip of the first type having at least a first electrical contact element disposed on a front side thereof and at least a second electrical contact element disposed on a back side thereof, the second electrical contact element being electrically coupled with a first electrically-conductive back side interconnect element, a portion of the interconnect element being outside of the hard molded compound and disposed on a back side of the eWLP package, the first electrical contact element being outside of the hard molded compound and disposed on a front side of the eWLP package;

an electrical interface on either the front side or the back side of the eWLP package; and

a carrier on which the eWLP package is mounted, the carrier having an electrical interface that is interfaced with the electrical interface of the eWLP package.

15. The eWLP assembly of claim 14, wherein the back side interconnect element comprises a semiconductor material that has been doped to increase an electrical conductivity of the semiconductor material.

16. The eWLP assembly of claim 15, wherein the semiconductor material is n-doped semiconductor material.

17. The eWLP assembly of claim 16, wherein the semiconductor material is n-doped silicon.

18. The eWLP assembly of claim 14, wherein the components further include an IC chip of a second type that is different from the first type, the IC chip of the second type having at least a first electrical contact element disposed on the front side thereof, and wherein each eWLP package includes at least one of the IC chips of the second type.

19. The eWLP assembly of claim 18, wherein a back side of each IC chip of the second type is outside of the hard molded compound and is disposed on the back side of the eWLP artificial wafer, and wherein a bulk material of the IC chip of the second type provides an electrically-conductive pathway between the front side of the eWLP wafer and the back side of the eWLP wafer.

20. The eWLP assembly of claim 19, wherein the back side of each IC chip of the second type has at least a second electrical contact element thereon, and wherein one or more p-type or n-type wells formed in the bulk material electrically isolate the first electrical contact element disposed on the front side of the IC chip of the second type from the second electrical contact element disposed on the back side of the IC chip of the second type.

21. The eWLP assembly of claim 18, wherein a back side of the IC chip of the second type has a second electrical contact element thereon, the second electrical contact element disposed on the back side of the IC chip of the second type being electrically coupled with a second electrically-conductive back side interconnect element, a portion of the second interconnect element being outside of the hard molded compound and disposed on the back side of the eWLP artificial wafer.

22. The eWLP assembly of claim 14, wherein the components further include a block of bulk material having a front side that is outside of the hard molded compound and is disposed on the front side of the eWLP artificial wafer and having a back side that is outside of the hard molded compound and is disposed on the back side of the eWLP artificial wafer, and wherein the bulk material provides an electrically-conductive pathway between the front side of the eWLP wafer and the back side of the eWLP wafer, and wherein each eWLP package includes at least one of the blocks of bulk material.

23. The eWLP assembly of claim 18, wherein the components further include an IC chip of a third type that is different from the first and second types, the IC chip of the third type having at least a first electrical contact element disposed on the front side thereof, and wherein each eWLP package includes at least one of the IC chips of the third type.

24. The eWLP assembly of claim 14, wherein the IC chip of the first type is a receiver chip comprising one or more photosensors for sensing ambient light, and wherein the IC chip is also a processor chip that processes electrical sense signals produced by said one or more photosensors to determine a level of ambient light being sensed by said one or more photosensors.

25. The eWLP assembly of claim 18, wherein the IC chips of the first and second types are optoelectronic receiver and transmitter IC chips, respectively, and wherein the transmitter IC chip emits light of a particular wavelength or range of wavelengths, and wherein the receiver IC chip detects light of said particular wavelength or range of wavelengths reflected from a reflective object, and wherein at least one of the IC chips is also a processor IP chip comprising processing circuitry for processing electrical sense signals produced by the receiver IC chip to determine at least one of a proximity of the eWLP assembly to the object, a distance of the eWLP assembly from the object, a gesture made by the object, and a spatial position of the object in 3-dimensional (3-D) space.

26. The eWLP assembly of claim 23, wherein the IC chips of the first and second types are optoelectronic receiver and transmitter IC chips, respectively, and the IC chip of the third type is a processor IP chip comprising processing circuitry, and wherein the transmitter IC chip emits light of a particular wavelength or range of wavelengths, and wherein the receiver IC chip detects light of said particular wavelength or range of wavelengths reflected from a reflective object, and wherein the processing circuitry of the processor chip processes electrical sense signals produced by the receiver IC chip to determine at least one of a proximity of the eWLP assembly to the object, a distance of the eWLP assembly from the object, a gesture made by the object, and a spatial position of the object in 3-dimensional (3-D) space.

27. The eWLP assembly of claim 23, wherein the IC chips of the first, second and third types are a first optoelectronic receiver IC chip, an optoelectronic transmitter IC chip, and a second optoelectronic receiver IC chip, respectively, and wherein the transmitter IC chip emits light of a particular wavelength or range of wavelengths, and wherein the first receiver IC chip detects light of said particular wavelength or range of wavelengths reflected from a reflective object, and wherein the second receiver IC chip senses ambient light, and wherein at least one of the IC chips is also a processor chip comprises processing circuitry that processes electrical sense signals produced by the second receiver chip to determine a level of ambient light being sensed by the second receiver IC chip.

28. The eWLP assembly of claim 27, and wherein the processing circuitry processes electrical sense signals produced by the first receiver IC chip to determine at least one of a proximity of the eWLP assembly to the object, a distance of the eWLP assembly from the object, a gesture made by the object, and a spatial position of the object in 3-dimensional (3-D) space.

29. The eWLP assembly of claim 14, wherein the carrier is a circuit board having electrical conductors formed therein and having one or more electrical contacts disposed on a surface thereof, said one or more electrical contacts disposed on the surface of the circuit board electrically interfacing with said at least a first electrical contact element of the IC chip of the first type.

30. The eWLP assembly of claim 14, wherein the carrier is a transparent substrate having electrical conductors disposed therein and having one or more electrical contacts disposed on a surface thereof, said one or more electrical contacts disposed on the surface of the substrate electrically interfacing with said at least a first electrical contact element of the IC chip of the first type.

31. An embedded Wafer-Level Packaging (eWLP) method comprising:

forming an eWLP artificial wafer comprising having a front side, a back side, and a plurality of interconnect elements extending between the front side and the back side of the eWLP artificial wafer, each interconnect element having a first end disposed on a front side of the eWLP artificial wafer outside of the wafer and having a second end disposed on a back side of the eWLP artificial wafer outside of the wafer, each interconnect element comprising a semiconductor material that has been doped to increase an electrical conductivity of the semiconductor material such that the interconnect element acts as an electrical interconnect between the front side of the eWLP artificial wafer and the back side of the eWLP artificial wafer.