Integrated circuit device

• US 9,443,843 B2
• Filed: 10/29/2015
• Issued: 09/13/2016
• Est. Priority Date: 11/21/2014
• Status: Active Grant

• Current Assignee: VIA Labs Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Chang, Yin-Ku, Lee, Sheng-Yuan
• Primary Examiner(s): Seven, Evren
• Application Number:
  US14/926,888
• Publication Number:
  US 20160148926A1
• Time in Patent Office: 320 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
• CPC Class Codes: H01L 27/0641 without components of the field effect type
• CPC Class Codes: H01L 27/0788 comprising combinations of diodes or capacitors or resistors
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/93 Variable capacitance diodes, e.g. varactors
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention provides an integrated circuit device. The integrated circuit device includes a substrate. A first capacitor is disposed on the substrate. A first metal pattern is coupled to a first electrode of the first capacitor. A second metal pattern is coupled to a first electrode of the second capacitor. A third metal pattern is disposed over the first and second metal patterns. The third metal pattern covers the first capacitor, the first metal pattern and the second metal pattern. The third metal pattern is electrically grounding. An inductor is disposed over the third metal pattern.

Claims

1. An integrated circuit device, comprising:

a substrate;

a first capacitor disposed on the substrate;

a first metal pattern coupled to a first electrode of the first capacitor;

a second metal pattern coupled to a second electrode of the first capacitor;

a third metal pattern disposed over the first and second metal patterns and covering the first capacitor, the first metal pattern, and the second metal pattern, wherein the third metal pattern is coupled to ground; and

an inductor disposed over the third metal pattern,

wherein the first capacitor comprises;

a first oxide layer disposed among the first, second, and third metal patterns, wherein the first metal pattern serves as the first electrode of the first capacitor, the second metal pattern serves as the second electrode of the first capacitor.

2. The integrated circuit device as claimed in claim 1, further comprising:

a plurality of metal layers disposed on the substrate, wherein the third metal pattern and the first metal pattern respectively occupy different metal layers of the metal layers, and wherein the third metal pattern and the second metal pattern respectively occupy different metal layers of the metal layers.

3. The integrated circuit device as claimed in claim 1, wherein the third metal pattern is disposed directly under the inductor, wherein the first metal pattern and the second metal pattern are disposed directly under the third metal pattern, and wherein a boundary of the first metal pattern and a boundary of the second metal pattern are respectively positioned within a boundary of the third metal pattern in a plane view.

4. The integrated circuit device as claimed in claim 1, wherein the first, second, and third metal patterns are separated from and parallel to one another.

5. The integrated circuit device as claimed in claim 1, wherein the first capacitor is a first metal-oxide-metal (MOM) capacitor.

6. The integrated circuit device as claimed in claim 1, wherein the first metal pattern and the second metal pattern belong to a first metal layered level, the third metal pattern belongs to a second metal layered level, which is different from the first metal layered level.

7. The integrated circuit device as claimed in claim 1, wherein the first metal pattern belongs to a first metal layered level, the second metal pattern belongs to a second metal layered level, and the third metal pattern belongs to a third metal layered level, wherein the first, second, and third metal layered levels are different from one another.

8. The integrated circuit device as claimed in claim 1, further comprising:

a second capacitor disposed between the substrate and the third metal pattern.

9. The integrated circuit device as claimed in claim 8, wherein the second capacitor is a metal-oxide-semiconductor (MOS) varactor.

10. The integrated circuit device as claimed in claim 9, wherein the second capacitor is a first metal-oxide-semiconductor (MOS) capacitor, and the first metal-oxide-semiconductor (MOS) capacitor comprises:

a first well doped region extended from a surface of the substrate to a portion of the substrate;

a first gate structure disposed on the first well doped region; and

a source and a drain respectively positioned on two opposite sides of the first gate structure, wherein the first gate structure serves as the first electrode, the source and the drain serve as the second electrode.

11. The integrated circuit device as claimed in claim 10, wherein the first well doped region is formed by doping an impurity within the substrate.

12. The integrated circuit device as claimed in claim 11, wherein the impurity is a p-type impurity or an n-type impurity.

13. The integrated circuit device as claimed in claim 10, further comprising:

a third capacitor disposed between the substrate and the third metal pattern.

14. The integrated circuit device as claimed in claim 13, wherein the third capacitor is a second metal-oxide-semiconductor (MOS) capacitor, which is positioned parallel to the first metal-oxide-semiconductor (MOS) capacitor, wherein a second well doped region of the second metal-oxide-semiconductor (MOS) capacitor is separated from the first well doped region.

15. The integrated circuit device as claimed in claim 14, wherein the third metal pattern comprises a first metal trace and a second metal trace, and the first metal trace fully covers the first well doped region, and the second metal trace fully covers the second well doped region in a plane view.

16. The integrated circuit device as claimed in claim 15, wherein the substrate is exposed to a region positioned between the first and second metal traces.

17. The integrated circuit device as claimed in claim 1, further comprising;

a fourth metal pattern between the first metal pattern and the third metal pattern;

a fifth metal pattern between the second metal pattern and the third metal pattern; and

the first oxide layer disposed among the first, second, third, fourth and fifth metal patterns, wherein the first and fifth metal patterns serve as the first electrode of the first capacitor, the second and fourth metal patterns serve as the second electrode of the first capacitor.

18. The integrated circuit device as claimed in claim 17, further comprising:

a plurality of metal layers disposed on the substrate, wherein the third metal pattern, the first metal pattern and the fourth metal pattern respectively occupy different metal layers of the metal layers, and wherein the third metal pattern, the second metal pattern and the fifth metal pattern respectively occupy different metal layers of the metal layers.

19. The integrated circuit device as claimed in claim 1, further comprising:

a second capacitor disposed between the substrate and the first capacitor.

20. The integrated circuit device as claimed in claim 19, wherein the second capacitor is a metal-oxide-semiconductor (MOS) varactor or a first metal-oxide-semiconductor (MOS) capacitor.