Vertical fin eDRAM

• US 9,443,857 B2
• Filed: 12/05/2014
• Issued: 09/13/2016
• Est. Priority Date: 12/05/2014
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Anderson, Brent A., Barth, John E. Jr., Nowak, Edward J.
• Primary Examiner(s): FERNANDES, ERROL V
• Application Number:
  US14/561,999
• Publication Number:
  US 20160163712A1
• Time in Patent Office: 648 Days
• Field of Search: 257/68, 257/71, 257/301, 438/243, 438/386
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/02598 monocrystalline
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02636 Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 12/0387 Making the trench
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/36 the transistor being a FinFET
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/373 the capacitor extending under or around the transistor
• CPC Class Codes: H10B 12/482 Bit lines

Abstract

Systems and methods of forming semiconductor devices. A trench capacitor comprising deep trenches is formed in an n+ type substrate. The deep trenches have a lower portion partially filled with a trench conductor surrounded by a storage dielectric. A polysilicon growth is formed in an upper portion of the deep trenches. The semiconductor device includes a single-crystal semiconductor having an angled seam separating a portion of the polysilicon growth from an exposed edge of the deep trenches. A word-line is wrapped around the single-crystal semiconductor. A bit-line overlays the single-crystal semiconductor.

Claims

1. A semiconductor device comprising:

a trench capacitor comprising deep trenches formed in a n+ type substrate, said deep trenches having a lower portion partially filled with a trench conductor surrounded by a storage dielectric;

a polysilicon growth formed in an upper portion of said deep trenches;

a single-crystal semiconductor having a seam separating a portion of said polysilicon growth from an exposed edge of said deep trenches, said seam being at an acute angle from said exposed edge;

a word-line wrapped around said single-crystal semiconductor; and

a bit-line overlaying said single-crystal semiconductor.

2. The semiconductor device according to claim 1, further comprising:

a buried oxide (BOX) layer, and

a silicon on oxide (SOI) layer,

said trench conductor extending into said BOX layer.

3. The semiconductor device according to claim 2, said seam separating a portion of said polysilicon growth and an exposed edge of said SOI layer.

4. The semiconductor device according to claim 2, said single-crystal semiconductor being selectively grown from said SOI layer.

5. The semiconductor device according to claim 1, further comprising:

fins formed in said single-crystal semiconductor; and

nodes comprising doped silicon epitaxially grown on exposed ends of said fins,

said bit-line contacting said nodes.

6. The semiconductor device according to claim 1, further comprising at least one oxide layer between said word-line and said bit-line.

7. The semiconductor device according to claim 1, further comprising:

a gate stack comprising;

said word-line;

an insulator layer; and

a doped silicon node contacting said bit-line.

8. A semiconductor device comprising:

a substrate comprising;

a silicon layer,

a buried oxide (BOX) layer, and

a silicon on oxide (SOI) layer, said BOX layer being between said silicon layer and said SOI layer;

a trench capacitor comprising deep trenches through said BOX layer and said SOI layer and partially into said silicon layer, said deep trenches having a lower portion partially filled with a trench conductor surrounded by a storage dielectric, said trench conductor extending into said BOX layer;

a polysilicon growth extending from said trench conductor in an upper portion of said deep trenches;

a single-crystal semiconductor extending from an exposed edge of said SOI layer; and

a seam separating a portion of said polysilicon growth from said exposed edge of said SOI layer.

9. The semiconductor device according to claim 8, said seam being at an acute angle from said exposed edge.

10. The semiconductor device according to claim 8, further comprising:

fins formed in said single-crystal semiconductor.

11. The semiconductor device according to claim 10, further comprising:

nodes comprising doped silicon epitaxially grown on exposed ends of said fins.

12. The semiconductor device according to claim 11, further comprising:

a bit-line contacting said nodes.

13. The semiconductor device according to claim 12, further comprising:

a word-line wrapped around said single-crystal semiconductor.

14. The semiconductor device according to claim 13, further comprising an oxide layer between said word-line and said bit-line.