Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step

• US 9,443,873 B1
• Filed: 12/14/2015
• Issued: 09/13/2016
• Est. Priority Date: 12/14/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kerber, Pranita, Ouyang, Qiqing C., Reznicek, Alexander, Schepis, Dominic J.
• Primary Examiner(s): Roman, Angel
• Application Number:
  US14/967,526
• Time in Patent Office: 274 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/7849 the means being provided under the channel

Abstract

A method of making a semiconductor device includes forming a first silicon germanium layer on a substrate, the first silicon germanium layer forming a portion of a first transistor; forming a second silicon germanium layer on the substrate adjacent to the first silicon germanium layer, the second silicon germanium layer forming a portion of a second transistor and having a germanium content that is different than the first silicon germanium layer and a thickness that is substantially the same; growing by an epitaxial process a compressively strained silicon germanium layer on the first silicon germanium layer, and a tensile strained silicon germanium layer on the second silicon germanium layer; patterning a first fin in the compressively strained silicon germanium layer and the first silicon germanium layer; and patterning a second fin in the tensile strained silicon germanium layer and the second silicon germanium layer.

Claims

1. A method of making a semiconductor device, comprising:

forming a first silicon germanium layer on a substrate, the first silicon germanium layer forming a portion of a first transistor;

forming a second silicon germanium layer on the substrate adjacent to the first silicon germanium layer, the second silicon germanium layer forming a portion of a second transistor and having a germanium content that is different than the first silicon germanium layer of the first transistor, and the first silicon germanium layer and the second silicon germanium layer having substantially the same thickness;

growing by an epitaxial process a compressively strained silicon germanium layer on the first silicon germanium layer, and a tensile strained silicon germanium layer on the second silicon germanium layer;

patterning a first fin in the compressively strained silicon germanium layer and the first silicon germanium layer of the first transistor; and

patterning a second fin in the tensile strained silicon germanium layer and the second silicon germanium layer of the second transistor.

2. The method of claim 1, wherein the second silicon germanium layer has a germanium content that is greater than the tensile strained silicon germanium layer.

3. The method of claim 1, wherein the compressively strained strained silicon germanium layer and the tensile strained silicon germanium layer have a germanium content that is substantially the same.

4. The method of claim 1, wherein the compressively strained silicon germanium layer and the tensile strained silicon germanium layer are formed in a single step.

5. The method of claim 1, wherein the first transistor is a pFET, and the second transistor is an nFET.

6. The method of claim 1, wherein the first silicon germanium layer of the first transistor and the second silicon germanium layer of the second transistor are relaxed.

7. A semiconductor device, comprising:

a substrate comprising a semiconductor material;

a buried dielectric layer arranged on the substrate;

a first transistor comprising a fin arranged on the buried dielectric layer, the fin having a silicon germanium layer arranged on the buried dielectric layer and a compressively strained silicon germanium layer arranged on the silicon germanium layer;

a second transistor comprising a fin arranged on the buried dielectric layer, the fin having a silicon germanium layer arranged on the buried dielectric layer and a tensile strained silicon germanium layer arranged on the silicon germanium layer; and

a gate positioned on the fin of the first transistor and the fin of the second transistor;

wherein the compressively strained strained silicon germanium layer and the tensile strained silicon germanium layer have a germanium content that is substantially the same.

8. The semiconductor device of claim 7, wherein the silicon germanium layer of the first transistor and the silicon germanium layer of the second transistor are relaxed.

9. The semiconductor device of claim 7, wherein the silicon germanium layer of the first transistor has a germanium content that is less than the germanium content of the compressively strained silicon germanium layer.

10. The semiconductor device of claim 7, wherein the silicon germanium layer of the second transistor has a germanium content that is greater than the germanium content of the tensile strained silicon germanium layer.

11. The semiconductor device of claim 7, wherein the germanium content of the tensile strained silicon germanium layer and the compressively strained silicon germanium layer is less than a germanium content of the silicon germanium layer of the second transistor, and greater than a germanium content of the silicon germanium layer of the first transistor.

12. The semiconductor device of claim 7, wherein the first transistor is a pFET, and the second transistor is an nFET.

13. The semiconductor device of claim 7, wherein the compressively strained silicon germanium layer has at least 1% compressive strain.

14. The semiconductor device of claim 7, wherein the tensile strained silicon germanium layer has at least 1% tensile strain.

15. A semiconductor device, comprising:

a substrate comprising a semiconductor material;

a buried dielectric layer arranged on the substrate;

a first transistor comprising a fin arranged on the buried dielectric layer, the fin having a first relaxed silicon germanium layer arranged on the buried dielectric layer and a compressively strained silicon germanium layer arranged on the silicon germanium layer;

a second transistor comprising a fin arranged on the buried dielectric layer, the fin having a second relaxed silicon germanium layer arranged on the buried dielectric layer and a tensile strained silicon germanium layer arranged on the silicon germanium layer, the second relaxed silicon germanium layer comprising a germanium content that is greater than the first relaxed silicon germanium layer; and

a gate arranged on the fin of the first transistor and the fin of the second transistor;

wherein the compressively strained strained silicon germanium layer and the tensile strained silicon germanium layer have a germanium content that is substantially the same.

16. The semiconductor device of claim 15, wherein the first transistor is a pFET, and the second transistor is an nFET.

17. The semiconductor device of claim 15, wherein wherein the germanium content of the tensile strained silicon germanium layer and the compressively strained silicon germanium layer is less than a germanium content of the second relaxed silicon germanium layer of the second transistor, and greater than a germanium content of the first relaxed silicon germanium layer of the first transistor.

18. The semiconductor device of claim 15, wherein the thickness of the first relaxed silicon germanium layer of the first transistor is in a range from about 6 to about 1000 nm.

19. The semiconductor device of claim 15, wherein the thickness of the second relaxed silicon germanium layer of the second transistor is in a range from about 6 to about 1000 nm.

20. The semiconductor device of claim 15, wherein the thickness of each of the compressively strained silicon germanium layer and the tensile strained silicon germanium layer is in a range from about 10 to about 50 nm.