Methods of forming printable integrated circuit devices and devices formed thereby
First Claim
1. A wafer of integrated circuit devices, comprising:
- a substrate;
a plurality of integrated circuits, each integrated circuit suspended entirely over a gap between the respective integrated circuit and the substrate and comprising a semiconductor active layer;
one or more multi-layer electrical interconnect networks, each multi-layer electrical interconnect network disposed on the semiconductor active layer of a corresponding integrated circuit;
a plurality of anchors disposed on the substrate and separated by the gaps, each anchor disposed adjacent to at least one integrated circuit; and
a plurality of tethers, each tether extending between at least one of the integrated circuits and at least one of the anchors to attach the integrated circuits to the anchors.
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0 Petitions
Accused Products
Abstract
Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.
127 Citations
20 Claims
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1. A wafer of integrated circuit devices, comprising:
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a substrate; a plurality of integrated circuits, each integrated circuit suspended entirely over a gap between the respective integrated circuit and the substrate and comprising a semiconductor active layer; one or more multi-layer electrical interconnect networks, each multi-layer electrical interconnect network disposed on the semiconductor active layer of a corresponding integrated circuit; a plurality of anchors disposed on the substrate and separated by the gaps, each anchor disposed adjacent to at least one integrated circuit; and a plurality of tethers, each tether extending between at least one of the integrated circuits and at least one of the anchors to attach the integrated circuits to the anchors. - View Dependent Claims (2, 4, 5, 6, 7, 8)
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3. A wafer of integrated circuit devices, comprising:
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a substrate; a plurality of integrated circuits, each integrated circuit comprising a semiconductor active layer; one or more multi-layer electrical interconnect networks, each multi-layer electrical interconnect network disposed on the semiconductor active layer of a corresponding integrated circuit; a plurality of anchors disposed on the substrate, each anchor disposed adjacent to at least one integrated circuit, wherein the plurality of anchors are inorganic semiconductor anchors; and a plurality of tethers, each tether extending between at least one of the integrated circuits and at least one of the anchors.
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9. A wafer of integrated circuit devices, comprising:
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a substrate; a plurality of integrated circuits, each integrated circuit comprising a semiconductor active layer; one or more multi-layer electrical interconnect networks, each multi-layer electrical interconnect network disposed on the semiconductor active layer of a corresponding integrated circuit; a plurality of anchors disposed on the substrate, each anchor disposed adjacent to at least one integrated circuit; and plurality of tethers, each tether extending between at least one of the integrated circuits and at least one of the anchors, wherein the plurality of tethers and the semiconductor active layer of each of the integrated circuits collectively are formed of a patterned semiconductor layer. - View Dependent Claims (10, 11)
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12. A wafer of integrated circuit devices, comprising:
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a substrate; a patterned sacrificial layer on the substrate; a patterned semiconductor active layer on the patterned sacrificial layer; and a patterned field oxide layer on the patterned semiconductor layer, a plurality of integrated circuits, each integrated circuit comprising a semiconductor-on-insulator substrate collectively defined by the patterned sacrificial layer, the patterned semiconductor layer, and the patterned field oxide layer collectively; one or more anchors on the substrate; a plurality of tethers, wherein each integrated circuit is connected to at least one of the one or more anchors by one or more tethers; a plurality of multi-layer electrical interconnect networks, wherein one or more multi-layer electrical interconnect networks is disposed on the active semiconductor layer of each respective integrated circuit, and a patterned capping layer at least partially on the multi-layer electrical interconnect networks, an upper surface of the semiconductor active layers, and a surface of the anchors to thereby define a plurality of suspended integrated circuits that are individually encapsulated by the patterned capping layer. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification