X-Y address type solid state image pickup device and method of producing the same

• US 9,443,897 B2
• Filed: 02/18/2015
• Issued: 09/13/2016
• Est. Priority Date: 07/11/2001
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Suzuki, Ryoji, Mabuchi, Keiji, Mori, Tomonori
• Primary Examiner(s): Henry, Caleb
• Assistant Examiner(s): Belousov, Alexander
• Application Number:
  US14/625,179
• Publication Number:
  US 20150243692A1
• Time in Patent Office: 573 Days
• Field of Search: 257/294, 257/184, 257/187, 257/292, 257/444, 257/E31.058
• US Class Current: 1/1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 31/02164 for shielding light, e.g. light blocking layers, cold shields for infrared detectors
• CPC Class Codes: H01L 31/0232 Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20
• CPC Class Codes: H01L 31/02327 the optical elements being integrated or being directly associated to the device, e.g. back reflectors optical coatings H01L31/0216
• CPC Class Codes: H04N 25/79 Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein. and visible light is taken in from the other side of the silicon layer, namely, from the side (back side) opposite to the wiring layer. wiring can be made without taking a light-receiving surface into account, and the degree of freedom in wiring for the pixels is enhanced.

Claims

1. An image sensor comprising:

a light-shielding film that is impenetrable to light, an opening portion is a hole that extends through the light-shielding film;

a floating diffusion at a first surface side of a semiconductor layer, a light-receiving surface side of the semiconductor layer is between the light-shielding film and the first surface side;

a transfer transistor gate electrode in a wiring layer, the first surface side is between the wiring layer and the light-receiving surface side; and

a photo-electric conversion device in the semiconductor layer, the transfer transistor gate electrode is between the floating diffusion and the photo-electric conversion device in a plan view of the image sensor.

2. The image sensor of claim 1, wherein the image sensor is a back-illuminated type CMOS image sensor.

3. The image sensor of claim 1, wherein the light-shielding layer is a metallic layer.

4. The image sensor of claim 1, wherein the photo-electric conversion device extends from the first surface side to the light-receiving surface side.

5. The image sensor of claim 1, further comprising:

an insulating film between said light-shielding film and said light-receiving surface.

6. The image sensor of claim 1, further comprising:

a substrate support member, the wiring layer is between the semiconductor layer and the substrate support member.

7. The image sensor of claim 1, wherein the photo-electric conversion device is configured to receive incident light.

8. The image sensor of claim 7, wherein the incident light is transmissible through the opening portion and onto the photo-electric conversion device.

9. The image sensor of claim 7, wherein the photo-electric conversion device is configured to convert the incident light into a signal charge.

10. The image sensor of claim 7, further comprising:

a micro-lens, the opening portion is between the photo-electric conversion device and the micro-lens.

11. The image sensor of claim 10, wherein the opening portion is in optical alignment with the micro-lens and the photo-electric conversion device.

12. The image sensor of claim 10, wherein the incident light is transmissible through the micro-lens and onto the photo-electric conversion device.

13. The image sensor of claim 1, further comprising:

well regions of a first conductivity type in the semiconductor layer, the photo-electric conversion device is between one of the well regions and another of the well regions.

14. The image sensor of claim 13, wherein the light-receiving surface side is a layer of the first conductivity type.

15. The image sensor of claim 13, wherein the layer of the first conductivity type is P-type.

16. The image sensor of claim 13, wherein the floating diffusion is of a second conductivity type, the second conductivity type is opposite to the first conductivity type.

17. The image sensor of claim 16, wherein the second conductivity type is N-type.

18. The image sensor of claim 1, further comprising:

an amplifying transistor, the floating diffusion is directly electrically connected a amplifying transistor gate electrode.

19. The image sensor of claim 18, wherein a reset transistor gate electrode is between the floating diffusion and a source/drain region in the plan view of the image sensor.

20. The image sensor of claim 19, further comprising:

a power source electrically connected to the source/drain region.

21. The image sensor of claim 19, wherein the amplifying transistor gate electrode is between the source/drain region and a different source/drain region in the plan view of the image sensor.

22. The image sensor of claim 21, wherein an address transistor gate electrode is between the different source/drain region and another source/drain region in the plan view of the image sensor.