Semiconductor device with field electrode

• US 9,443,972 B2
• Filed: 11/30/2011
• Issued: 09/13/2016
• Est. Priority Date: 11/30/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Blank, Oliver
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): KOO, LAMONT B
• Application Number:
  US13/307,465
• Publication Number:
  US 20130137230A1
• Time in Patent Office: 1,749 Days
• Field of Search: 438/270, 257/E21.41
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A method of producing a semiconductor device includes providing a semiconductor body having a first surface and a dielectric layer arranged on the first surface and forming at least one first trench in the dielectric layer. The at least one first trench extends to the semiconductor body and defines a dielectric mesa region in the dielectric layer. The method further includes forming a second trench in the dielectric mesa region distant to the at least one first trench, forming a semiconductor layer on uncovered regions of the semiconductor body in the at least one first trench and forming a field electrode in the second trench.

Claims

1. A method of producing a semiconductor device, the method comprising:

providing a semiconductor body having a first surface and a dielectric layer arranged on the first surface;

forming at least one first trench in the dielectric layer, the at least one first trench extending to the semiconductor body and defining a dielectric mesa region in the dielectric layer;

forming a second trench in the dielectric layer, distant to the at least one first trench, leaving portions of the dielectric layer immediately adjacent the second trench in the dielectric mesa region, wherein the second trench is formed such that a bottom of the second trench is arranged within the dielectric layer;

forming a semiconductor layer in the at least one first trench, on regions of the semiconductor body that are not covered by the dielectric layer in the at least one first trench; and

forming a field electrode in the second trench.

2. The method of claim 1, wherein the semiconductor layer is a monocrystalline semiconductor layer.

3. The method of claim 2, wherein forming the semiconductor layer includes a selective epitaxial growth process.

4. The method of claim 1, wherein the at least one first trench and the second trench are formed with a common etching process, using one etch mask.

5. The method of claim 1, wherein the second trench is formed to extend to the semiconductor body.

6. The method of claim 1, wherein the at least one first trench and the second trench have vertical sidewalls.

7. The method of claim 1, wherein at least one of the at least one first trench and the second trench have tapered sidewalls.

8. The method of claim 1, wherein forming the at least one first trench comprises forming a ring-shaped first trench defining the dielectric mesa region.

9. The method of claim 1, wherein forming the at least one first trench comprises forming two distant first trenches, wherein the dielectric mesa region is formed between the two distant first trenches.

10. The method of claim 1, wherein the semiconductor layer completely fills the at least one first trench.

11. The method of claim 1, wherein the semiconductor layer is epitaxially grown by a selective epitaxial growth process.

12. The method of claim 1, wherein the semiconductor layer has a basic doping of a first doping type, the method further comprising:

forming a body region of a second doping type in the semiconductor layer;

forming a source region of the first doping type in the body region; and

forming a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric.

13. The method of claim 12, wherein forming the gate electrode comprises forming the gate electrode in a trench in the semiconductor layer distant to the dielectric mesa region.

14. The method of claim 12, wherein forming the gate electrode comprises forming the gate electrode above the semiconductor layer.

15. The method of claim 12, wherein forming the gate electrode comprises:

forming at least one third trench in the dielectric mesa region distant to the field electrode; and

forming the gate electrode in the at least one third trench.

16. The method of claim 15, further comprising:

forming the at least one third trench such that a first sidewall of the at least one third trench adjoins the semiconductor layer; and

forming a gate dielectric on the first sidewall of the at least one third trench before forming the gate electrode.