System and method for dynamically biasing oscillators for optimum phase noise

• US 9,444,400 B2
• Filed: 03/23/2015
• Issued: 09/13/2016
• Est. Priority Date: 01/09/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Taghivand, Mazhareddin, Johansen, Keplin Victor
• Primary Examiner(s): Gannon, Levi
• Application Number:
  US14/666,084
• Publication Number:
  US 20160204738A1
• Time in Patent Office: 540 Days
• Field of Search: 331/117.FE, 331/117.R, 331/177.V, 331/185, 331/186
• US Class Current: 1/1
• CPC Class Codes: H03B 5/1203 the amplifier being a single transistor
• CPC Class Codes: H03B 5/1206 using multiple transistors for amplification
• CPC Class Codes: H03B 5/1209 the amplifier having two current paths operating in a differential manner and a current source or degeneration circuit in common to both paths, e.g. a long-tailed pair. H03B5/1215 takes precedence
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/1243 the means comprising voltage variable capacitance diodes
• CPC Class Codes: H03B 5/1262 the means comprising switched elements
• CPC Class Codes: H03B 5/1265 switched capacitors
• CPC Class Codes: H03B 5/129 the parameter being a bias voltage or a power supply

Abstract

Systems and methods for biasing frequency oscillators to minimize phase noise are disclosed. The system may comprise a tank circuit having an inductor, at least a first coupling capacitor and a second coupling capacitor. The system may further comprise a varactor circuit electrically connected to the first coupling capacitor and the second coupling capacitor. The system may further comprise at least one first metal oxide semiconductor (MOS) device electrically connected in shunt with the tank circuit and a bias voltage. The at least one first MOS device may be electrically connected to a first gate bias voltage configured to bias the at least one first MOS device such that a first gate-to-source voltage of the at least one first MOS device remains below the first threshold voltage.

Claims

1. A frequency oscillator comprising:

a tank circuit having an inductor, a first coupling capacitor, and a second coupling capacitor;

a varactor circuit electrically coupled to the first coupling capacitor and the second coupling capacitor;

a first MOS device having a first gate, a first drain, and a first source, the first source being electrically coupled to the varactor circuit, and the first gate being electrically coupled to the first drain;

a second MOS device having a second gate, a second drain, and a second source, the second source being electrically coupled to the varactor circuit opposite the first source and the second gate being electrically coupled to the second drain;

a first input electrically coupled to the first drain and the second drain operable to receive a first bias voltage; and

a second input electrically coupled to the first gate and the second gate to receive a first gate bias voltage.

2. The frequency oscillator of claim 1 further comprising:

a first coarse tuning capacitor electrically coupled to the first coupling capacitor and the inductor;

a second coarse tuning capacitor electrically coupled to the second coupling capacitor and the inductor;

a third MOS device having a third gate, a third drain, and a third source, the third drain being electrically coupled to the first coarse tuning capacitor;

a fourth MOS device having fourth gate, a fourth drain, and a fourth source, the fourth drain being electrically coupled to the second coarse tuning capacitor;

a band control input electrically coupled to the third source and the fourth source;

a third input electrically coupled to the third gate and the fourth gate to receive a second gate bias voltage.

3. The frequency oscillator of claim 2, wherein the band control input is electrically coupled to the third input.

4. The frequency oscillator of claim 2, wherein the band control input and the third input are configured to receive at least one bias voltage, the at least one bias voltage selected to negatively bias the third MOS device and the fourth MOS device.

5. The frequency oscillator of claim 2 further comprising a switch having a switch gate, a switch drain, and a switch source, the switch gate being electrically coupled to the band control input, the switch drain being electrically coupled to the first coarse tuning capacitor and the third MOS device, and the switch source being electrically coupled to the second coarse tuning capacitor and the fourth MOS device.

6. The frequency oscillator of claim 1, wherein the first input is electrically coupled to the second input, and wherein the first gate bias voltage is equal to the first bias voltage.

7. The frequency oscillator of claim 1, wherein the first input and the second input are configured to receive at least one bias voltage, the at least one bias voltage selected to negatively bias the first MOS device and the second MOS device.

8. The frequency oscillator of claim 1, wherein the first MOS device and the second MOS device are configured to bias the varactor circuit and isolate a phase noise contribution of the first MOS device and the second MOS device to an oscillation peak of an output of the frequency oscillator.

9. A frequency oscillator comprising:

a variable capacitance circuit;

a tank circuit having at least one inductor and at least one capacitor, the tank circuit being electrically coupled in parallel to the variable capacitance circuit;

a first MOS device having a first gate, a first source, and a first drain, the first source electrically coupled to the tank circuit and the variable capacitance circuit, and the first gate being electrically coupled to the first drain;

a second MOS device having a second gate, a second source, and a second drain, the second source electrically coupled to the tank circuit and the variable capacitance circuit, and the second gate being electrically coupled to the second drain;

a first input electrically coupled to the first drain and the second drain, and configured to receive a first bias voltage; and

a second input electrically coupled to the first gate and the second gate, the second input configured to receive a first gate bias voltage, the first gate bias voltage operable to bias the first MOS device such that a first gate-to-source voltage of the first MOS device remains below a first threshold voltage, and to bias the second MOS device such that a second gate-to-source voltage of the second MOS device remains below a second threshold voltage, when the frequency oscillator is in operation.

10. The frequency oscillator of claim 9, further comprising:

a first coarse tuning capacitor and a second coarse tuning capacitor electrically coupled to the tank circuit;

a third MOS device having a third gate, a third source, and a third drain, the third source electrically coupled to the first coarse tuning capacitor;

a fourth MOS device having a fourth gate, a fourth source, and a fourth drain, the fourth source electrically coupled to the second coarse tuning capacitor;

a band control input electrically coupled to the third drain and the fourth drain; and

a third input electrically coupled to the third gate and the fourth gate to receive a second gate bias voltage, the second gate bias voltage being configured to bias the third MOS device such that a third gate-to-source voltage remains below a third threshold voltage and to bias the fourth MOS device such that a fourth gate-to-source voltage remains below a fourth threshold voltage.

11. The frequency oscillator of claim 10, wherein the band control input is electrically coupled to the third input.

12. The frequency oscillator of claim 9, wherein the first input is electrically coupled to the second input, and wherein the first gate bias voltage is equal to the first bias voltage.

13. The frequency oscillator of claim 9, wherein the first input and the second input are configured to receive at least one bias voltage, the at least one bias voltage selected to negatively bias the first MOS device and the second MOS device.

14. A method for biasing an oscillator circuit, comprising:

generating an oscillating output using a tank circuit electrically coupled to a varactor circuit;

biasing the varactor circuit using a first MOS device having a first threshold voltage and a second MOS device having a second threshold voltage, the varactor circuit being electrically coupled to a first source of the first MOS device and to a second source of the second MOS device;

biasing the first MOS device and the second MOS device with a first gate bias voltage at a first gate of the first MOS device and at a second gate of the second MOS device;

electrically coupling the first gate of the first MOS device to a first drain of the first MOS device;

electrically coupling the second gate of the second MOS device to a second drain of the second MOS device; and

controlling a first transconductance of the first MOS device and a second transconductance of the second MOS device with a first bias voltage and the first gate bias voltage.

15. The method of claim 14, further comprising:

generating a digital clock signal using the tank circuit and a band control input, the tank circuit being electrically coupled to a first coarse tuning capacitor and a second coarse tuning capacitor;

biasing a third MOS device and a fourth MOS device with a second gate bias voltage at a third gate of the third MOS device and at a fourth gate of the fourth MOS device, the band control input being electrically coupled to a third source of the third MOS device and a fourth source of the fourth MOS device; and

controlling a third transconductance of the third MOS device and a fourth transconductance of the fourth MOS device using the band control input and the second gate bias voltage.

16. The method of claim 15 further comprising electrically coupling the band control input to the second gate bias voltage.

17. The method of claim 14, further comprising electrically coupling the first gate bias voltage to the first bias voltage.

18. The method of claim 14, wherein a difference between the first bias voltage and the first gate bias voltage is not greater than the first and second threshold voltages.

19. An apparatus for producing an oscillating frequency comprising:

a resonating means for storing energy at a resonant frequency, the resonating means having and at least one inductor and at least one capacitor;

a variable capacitance means having a first end and a second end, the first end and the second end being electrically coupled to the resonating means;

a first transistor means having a first gate, a first drain, and a first source, the first source being electrically coupled to the first end, and the first gate being electrically coupled to the first drain;

a second transistor means having a second gate, a second drain, and a second source, the second source being electrically coupled to the second end, and the second gate being electrically coupled to the second drain;

a first biasing means electrically coupled to the first drain and the second drain; and

a second biasing means electrically coupled to the first gate and the second gate.

20. The apparatus of claim 19, wherein the variable capacitance means comprises a varactor circuit having the first end and the second end, the first end being electrically coupled to a first coupling capacitor and the second end being electrically coupled to a second coupling capacitor.

21. The apparatus of claim 19, further comprising:

a third transistor means having a third gate, a third source, and a third drain, the third source electrically coupled to the resonating means;

a fourth transistor means having a fourth gate, a fourth source, and a fourth drain, the fourth source being electrically coupled to the resonating means;

a band control means electrically coupled to the third drain and the fourth drain; and

an input means electrically coupled to the third gate and the fourth gate to receive a third biasing means.

22. The apparatus of claim 21, wherein the third biasing means is configured to bias the third transistor means such that a third gate-to-source voltage remains below a third threshold voltage and to bias the fourth transistor means such that a fourth gate-to-source voltage remains below a fourth threshold voltage.

23. The apparatus of claim 21 further comprising a switching means having a switch source, a switch drain, and a switch gate, the switch gate being electrically coupled to the band control means, the switch drain being electrically coupled to the third transistor means and the resonating means, and the switch source being electrically coupled to the fourth transistor means and the resonating means.