Zero-crossing detection circuit and method for synchronous step-down converter

• US 9,444,441 B2
• Filed: 11/14/2014
• Issued: 09/13/2016
• Est. Priority Date: 11/22/2013
• Status: Active Grant

• Current Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Original Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Inventors: Hou, Jinzhao, Chen, Chen
• Primary Examiner(s): Dole, Timothy J
• Assistant Examiner(s): AHMED, YUSEF A
• Application Number:
  US14/541,428
• Publication Number:
  US 20150145489A1
• Time in Patent Office: 669 Days
• US Class Current: 1/1
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 5/1536 Zero-crossing detectors in measuring circuits G01R19/175
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

In one embodiment, a zero-crossing detection circuit for a synchronous step-down converter, can include: (i) a state determination circuit configured to compare a drain voltage of a synchronous transistor of the synchronous step-down converter against a reference voltage, and to generate a state digital signal indicative of whether a body diode of the synchronous transistor is turned on; (ii) a logic circuit configured to convert the state digital signal into a counting instruction signal; (iii) a plus-minus counter configured to generate a numerical signal in response to the counting instruction signal; (iv) a DAC configured to generate a correction analog signal based on the numerical signal; and (v) a zero-crossing comparator configured to receive the correction analog signal and the drain voltage of the synchronous transistor, and to provide a zero-crossing comparison signal to a driving circuit of the synchronous step-down converter.

Claims

1. A zero-crossing detection circuit for a synchronous step-down converter, the zero-crossing detection circuit comprising:

a) a state determination circuit configured to compare a drain voltage of a synchronous transistor of said synchronous step-down converter against a reference voltage, and to generate a state digital signal indicative of whether a body diode of said synchronous transistor is turned on;

b) a logic circuit configured to convert said state digital signal into a counting instruction signal;

c) a plus-minus counter configured to generate a numerical signal in response to said counting instruction signal;

d) a digital-analog converter configured to generate a correction analog signal based on said numerical signal;

e) a zero-crossing comparator configured to receive said correction analog signal and said drain voltage of said synchronous transistor, and to provide a zero-crossing comparison signal to a driving circuit of said synchronous step-down converter; and

f) a timing logic circuit configured to receive a first timing signal from said driving circuit, and to generate a second timing signal indicative of an operation time of a comparator, and a third timing signal indicative of an operation time of said logic circuit, wherein said second and third timing signals are respectively provided to said comparator and said logic circuit, and said first timing signal is provided to said plus-minus counter.

2. The zero-crossing detection circuit of claim 1, wherein said state determination circuit comprises said comparator configured to compare said drain voltage of said synchronous transistor against said reference voltage.

3. The zero-crossing detection circuit of claim 1, wherein said timing logic circuit is configured to receive said first timing signal, and to generate said second and third timing signals, and a fourth timing signal indicative of an operation time of said plus-minus counter.

4. The zero-crossing detection circuit of claim 1, wherein said logic circuit comprises a D flip-flop having a D terminal configured to receive a high level, a clock terminal configured to receive said state digital signal, a reset terminal configured to receive said third timing signal, and an output terminal configured to provide said counting instruction signal.

5. The zero-crossing detection circuit of claim 1, wherein said logic circuit comprises a RS flip-flop having an S terminal configured to receive said state digital signal, an R terminal configured to receive third timing signal, and an output terminal configured to provide said counting instruction signal.

6. The zero-crossing detection circuit of claim 1, wherein said digital-analog converter comprises a digital-analog converting block and a balancing block, said balancing block comprising a resistor coupled to ground, to a DC current source and said digital-analog converting block, and wherein said DC current source comprises a current direction that is opposite to a current direction in said digital-analog converting block.

7. A zero-crossing detection method for a synchronous step-down converter, the method comprising:

a) providing an initial value of a plus-minus counter to a digital-analog converter, and generating a correction analog signal via digital-analog conversion;

b) triggering a zero-crossing comparator at an initial threshold point, turning off a synchronous transistor, comparing a reference voltage against a drain voltage of said synchronous transistor to determine a comparison result, and determining whether a body diode of said synchronous transistor is turned on according to said comparison result;

c) converting, by a logic circuit, a state digital signal indicative of whether said body diode of said synchronous transistor is turned on to a counting instruction signal;

d) executing, by said plus-minus counter, said counting instruction signal, and generating a numerical signal indicative of an offset correction amount;

e) converting, by said digital-analog converter, said numerical signal to a correction analog signal indicative of an actual offset correction amount;

f) providing said correction analog signal and said drain voltage of said synchronous transistor to said zero-crossing comparator, and a zero-crossing comparison signal to a driving circuit of said synchronous step-down converter for turning off said synchronous transistor; and

g) receiving, by a timing logic circuit, a first timing signal from said driving circuit, generating a second timing signal indicative of an operation time of a comparator, and a third timing signal indicative of an operation time of said logic circuit, wherein said second and third timing signals are respectively provided to said comparator and said logic circuit, and said first timing signal is provided to said plus-minus counter.

8. The method of claim 7, wherein said digital-analog converter comprises a digital-analog converting block and a balancing block, said balancing block comprising a resistor coupled to ground, to a DC current source and said digital-analog converting block, and wherein said DC current source comprises a current direction that is opposite to a current direction in said digital-analog converting block.