Non-blocking power management for on-package input/output architectures
First Claim
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1. An apparatus, comprising:
- a first set of single-ended transmitter circuits on a first die, wherein the first set of single-ended transmitter circuits is to transmit data during a first operational state and a subset of the first set of single-ended transmitter circuits is to transmit data during a second operational state;
a first set of single-ended receiver circuits on a second die;
a first plurality of conductive lines between the first set of transmitter circuits and thefirst set of receiver circuits, wherein the lengths of the plurality of conductive lines are matched;
a second set of single-ended receiver circuits on the first die;
a second set of single-ended transmitter circuits on the second die, wherein the second set of single-ended transmitter circuits is to transmit data during a third operational state and a subset of the second set of single-ended transmitter circuits is to transmit data during a fourth operational state; and
wherein the first and fourth operational states are able to concurrently exist and/or the second and third operational states are able to concurrently exist and wherein one of the first and second die is a memory and the other of the first and second die is to read from and write to the memory and where the concurrent existence of the first and fourth operational states and/or the second and third operational states correspond to a write width that is different than a read width.
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Abstract
An on-package interface. A first set of single-ended transmitter circuits on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits on a second die. The receiver circuits have no termination and no equalization. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.
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Citations
20 Claims
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1. An apparatus, comprising:
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a first set of single-ended transmitter circuits on a first die, wherein the first set of single-ended transmitter circuits is to transmit data during a first operational state and a subset of the first set of single-ended transmitter circuits is to transmit data during a second operational state; a first set of single-ended receiver circuits on a second die; a first plurality of conductive lines between the first set of transmitter circuits and the first set of receiver circuits, wherein the lengths of the plurality of conductive lines are matched; a second set of single-ended receiver circuits on the first die; a second set of single-ended transmitter circuits on the second die, wherein the second set of single-ended transmitter circuits is to transmit data during a third operational state and a subset of the second set of single-ended transmitter circuits is to transmit data during a fourth operational state; and wherein the first and fourth operational states are able to concurrently exist and/or the second and third operational states are able to concurrently exist and wherein one of the first and second die is a memory and the other of the first and second die is to read from and write to the memory and where the concurrent existence of the first and fourth operational states and/or the second and third operational states correspond to a write width that is different than a read width. - View Dependent Claims (2, 3, 4, 5)
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6. A tablet computing device, comprising:
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a touch screen interface; a first set of single-ended transmitter circuits on a first die, wherein the first set of single-ended transmitter circuits is to transmit data during a first operational state and a subset of the first set of single-ended transmitter circuits is to transmit data during a second operational state; a first set of single-ended receiver circuits on a second die; a first plurality of conductive lines between the first set of transmitter circuits and the first set of receiver circuits, wherein the lengths of the plurality of conductive lines are matched; a second set of single-ended receiver circuits on the first die; a second set of single-ended transmitter circuits on the second die, wherein the second set of single-ended transmitter circuits is to transmit data during a third operational state and a subset of the second set of single-ended transmitter circuits is to transmit data during a fourth operational state; and wherein the first and fourth operational states are able to concurrently exist and/or the second and third operational states are able to concurrently exist and wherein one of the first and second die is a memory and the other of the first and second die is to read from and write to the memory and where the concurrent existence of the first and fourth operational states and/or the second and third operational states correspond to a write width that is different than a read width. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A system comprising:
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an omnidirectional antenna; a first set of single-ended transmitter circuits on a first die, wherein the first set of single-ended transmitter circuits is to transmit data during a first operational state and a subset of the first set of single-ended transmitter circuits is to transmit data during a second operational state; a first set of single-ended receiver circuits on a second die; and a first plurality of conductive lines between the first set of transmitter circuits and the first set of receiver circuits, wherein the lengths of the plurality of conductive lines are matched; a second set of single-ended receiver circuits on the first die; a second set of single-ended transmitter circuits on the second die, wherein the second set of single-ended transmitter circuits is to transmit data during a third operational state and a subset of the second set of single-ended transmitter circuits is to transmit data during a fourth operational state; and
,wherein the first and fourth operational states are able to concurrently exist and/or the second and third operational states are able to concurrently exist and wherein one of the first and second die is a memory and the other of the first and second die is to read from and write to the memory and where the concurrent existence of the first and fourth operational states and/or the second and third operational states correspond to a write width that is different than a read width. - View Dependent Claims (13, 14, 15, 16, 17)
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18. An apparatus, comprising:
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a first semiconductor die, comprising; a first set of single-ended transmitter circuits, wherein the first set of single-ended transmitter circuits is to transmit data to a second die during a first operational state and a subset of the first set of single-ended transmitter circuits is to transmit data to the second die during a second operational state; a first set of single-ended receiver circuits to receive data from a second die, wherein the first set of single-ended receiver circuits is to receive data from the second die during a third operational state and a subset of the second set of single-ended transmitter circuits is to receive data from the second die during a fourth operational state, wherein the first and fourth operational states are able to concurrently exist and/or the second and third operational states are able to concurrently exist; wherein one of the first and second die is a memory and the other of the first and second die is to read from and write to the memory and where the concurrent existence of the first and fourth operational states and/or the second and third operational states correspond to a write width that is different than a read width. - View Dependent Claims (19, 20)
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Specification