Non-blocking power management for on-package input/output architectures

• US 9,444,509 B2
• Filed: 09/27/2012
• Issued: 09/13/2016
• Est. Priority Date: 09/27/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hinck, Todd A.
• Primary Examiner(s): CASSITY, ROBERT A
• Application Number:
  US13/629,357
• Publication Number:
  US 20140085791A1
• Time in Patent Office: 1,447 Days
• Field of Search: 713/300
• US Class Current: 1/1
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/1637 Details related to the display arrangement, including those related to the mounting of the display in the housing
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: H04B 1/40 Circuits

Abstract

An on-package interface. A first set of single-ended transmitter circuits on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits on a second die. The receiver circuits have no termination and no equalization. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.

Claims

1. An apparatus, comprising:

a first set of single-ended transmitter circuits on a first die, wherein the first set of single-ended transmitter circuits is to transmit data during a first operational state and a subset of the first set of single-ended transmitter circuits is to transmit data during a second operational state;

a first set of single-ended receiver circuits on a second die;

a first plurality of conductive lines between the first set of transmitter circuits and the

first set of receiver circuits, wherein the lengths of the plurality of conductive lines are matched;

a second set of single-ended receiver circuits on the first die;

a second set of single-ended transmitter circuits on the second die, wherein the second set of single-ended transmitter circuits is to transmit data during a third operational state and a subset of the second set of single-ended transmitter circuits is to transmit data during a fourth operational state; and

wherein the first and fourth operational states are able to concurrently exist and/or the second and third operational states are able to concurrently exist and wherein one of the first and second die is a memory and the other of the first and second die is to read from and write to the memory and where the concurrent existence of the first and fourth operational states and/or the second and third operational states correspond to a write width that is different than a read width.

2. The apparatus of claim 1 wherein the subset of the first set of single-ended transmitter circuits comprises half of the first set of single-ended transmitter circuits.

3. The apparatus of claim 1 wherein the subset of the first set of single-ended transmitter circuits comprises one quarter of the first set of single-ended transmitter circuits.

4. The apparatus of claim 1, wherein the first set of single-ended transmitter circuits are impedance matched and have no equalization and, wherein the first set of single-ended receiver circuits have no termination and no equalization.

5. The apparatus of claim 1, wherein the first die comprises at least a processor core, the apparatus further comprising a touch screen interface coupled with the processor core.

6. A tablet computing device, comprising:

a touch screen interface;

a first set of single-ended transmitter circuits on a first die, wherein the first set of single-ended transmitter circuits is to transmit data during a first operational state and a subset of the first set of single-ended transmitter circuits is to transmit data during a second operational state;

a first set of single-ended receiver circuits on a second die;

a first plurality of conductive lines between the first set of transmitter circuits and the

first set of receiver circuits, wherein the lengths of the plurality of conductive lines are matched;

a second set of single-ended receiver circuits on the first die;

a second set of single-ended transmitter circuits on the second die, wherein the second set of single-ended transmitter circuits is to transmit data during a third operational state and a subset of the second set of single-ended transmitter circuits is to transmit data during a fourth operational state; and

wherein the first and fourth operational states are able to concurrently exist and/or the second and third operational states are able to concurrently exist and wherein one of the first and second die is a memory and the other of the first and second die is to read from and write to the memory and where the concurrent existence of the first and fourth operational states and/or the second and third operational states correspond to a write width that is different than a read width.

7. The tablet of claim 6 wherein the subset of the first set of single-ended transmitter circuits comprises half of the first set of single-ended transmitter circuits.

8. The tablet of claim 6 wherein the subset of the first set of single-ended transmitter circuits comprises one quarter of the first set of single-ended transmitter circuits.

9. The tablet of claim 6, wherein the first set of single-ended transmitter circuits are impedance matched and have no equalization and, wherein the first set of single-ended receiver circuits have no termination and no equalization.

10. The tablet of claim 6 further comprising an antenna for communication.

11. The tablet of claim 6 wherein the first die, the second die and the plurality of conductive lines are all disposed within a single integrated circuit package.

12. A system comprising:

an omnidirectional antenna;

a first set of single-ended transmitter circuits on a first die, wherein the first set of single-ended transmitter circuits is to transmit data during a first operational state and a subset of the first set of single-ended transmitter circuits is to transmit data during a second operational state;

a first set of single-ended receiver circuits on a second die; and

a first plurality of conductive lines between the first set of transmitter circuits and the

first set of receiver circuits, wherein the lengths of the plurality of conductive lines are matched;

a second set of single-ended receiver circuits on the first die;

a second set of single-ended transmitter circuits on the second die, wherein the second set of single-ended transmitter circuits is to transmit data during a third operational state and a subset of the second set of single-ended transmitter circuits is to transmit data during a fourth operational state; and

,

wherein the first and fourth operational states are able to concurrently exist and/or the second and third operational states are able to concurrently exist and wherein one of the first and second die is a memory and the other of the first and second die is to read from and write to the memory and where the concurrent existence of the first and fourth operational states and/or the second and third operational states correspond to a write width that is different than a read width.

13. The system of claim 12 wherein the subset of the first set of single-ended transmitter circuits comprises half of the first set of single-ended transmitter circuits.

14. The system of claim 12 wherein the subset of the first set of single-ended transmitter circuits comprises one quarter of the first set of single-ended transmitter circuits.

15. The system of claim 12, wherein the first set of single-ended transmitter circuits are impedance matched and have no equalization and, wherein the first set of single-ended receiver circuits have no termination and no equalization.

16. The system of claim 12, wherein the first die comprises at least a processor core, the apparatus further comprising a touch screen interface coupled with the processor core.

17. The system of claim 12 wherein the first die, the second die and the plurality of conductive lines are all disposed within a single integrated circuit package.

18. An apparatus, comprising:

a first semiconductor die, comprising;

a first set of single-ended transmitter circuits, wherein the first set of single-ended transmitter circuits is to transmit data to a second die during a first operational state and a subset of the first set of single-ended transmitter circuits is to transmit data to the second die during a second operational state;

a first set of single-ended receiver circuits to receive data from a second die, wherein the first set of single-ended receiver circuits is to receive data from the second die during a third operational state and a subset of the second set of single-ended transmitter circuits is to receive data from the second die during a fourth operational state, wherein the first and fourth operational states are able to concurrently exist and/or the second and third operational states are able to concurrently exist;

wherein one of the first and second die is a memory and the other of the first and second die is to read from and write to the memory and where the concurrent existence of the first and fourth operational states and/or the second and third operational states correspond to a write width that is different than a read width.

19. The apparatus of claim 18 further comprising the second die.

20. The apparatus of claim 19 wherein the first die and the second die are within a same semiconductor package.