Error recovery within integrated circuit

• US 9,448,875 B2
• Filed: 12/06/2013
• Issued: 09/20/2016
• Est. Priority Date: 03/20/2003
• Status: Expired due to Term

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.), Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.), Board of Regents of the University of Michigan (University of Michigan)
• Inventors: Flautner, Krisztian, Austin, Todd Michael, Blaauw, David Theodore, Mudge, Trevor Nigel, Bull, David
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Ahmed, Enam
• Application Number:
  US14/098,821
• Publication Number:
  US 20140181581A1
• Time in Patent Office: 1,019 Days
• Field of Search: 714/799
• US Class Current: 1/1
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/0706 the processing taking place on a specific hardware platform or in a specific software environment
• CPC Class Codes: G06F 11/0736 in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function testing or monitoring of automated control systems G05B23/02
• CPC Class Codes: G06F 11/0754 by exceeding limits
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1402 Saving, restoring, recovering or retrying
• CPC Class Codes: G06F 11/1604 where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware

Abstract

An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Claims

1. An integrated circuit for performing data processing, said integrated circuit comprising:

an error detector configured to detect errors in operation of said integrated circuit;

error-repair circuitry configured to repair errors in operation of said integrated circuit; and

a power supply configured to apply a power supply voltage to at least one portion of said integrated circuit, wherein;

said power supply is configured to vary an error rate within said at least one portion by varying said power supply voltage to said at least one portion;

said power supply voltage to said at least one portion is provided via one or more power gates configured to vary said power supply voltage to said at least one portion; and

said power supply is controlled to produce a finite non-zero error rate within said at least one portion.

2. The integrated circuit of claim 1, wherein said at least one portion is a power domain within said integrated circuit.

3. The integrated circuit of claim 1, comprising power supply control circuitry configured at least to control provision of said power supply via said one or more power gates.

4. The integrated circuit of claim 2, wherein said integrated circuit comprises a plurality of power domains with respective power supplies, said power supplies varying to vary power consumption of said integrated circuit.

5. The integrated circuit of claim 1, wherein said power supply includes is configured to apply a body bias voltage applied to said at least one portion.

6. The integrated circuit of claim 1, wherein at least some of said one or more power gates are controlled so as to switch off said power supply voltage supply therethrough.

14. The integrated circuit of claim 1, wherein the power supply comprises a supply voltage controller.

7. An integrated circuit for performing data processing, said integrated circuit comprising:

error detector means for detecting errors in operation of said integrated circuit;

error-repair means for repairing errors in operation of said integrated circuit; and

a power supply configured to apply a power supply voltage to at least one portion of said integrated circuit, wherein;

said power supply is configured to vary an error rate within said at least one portion by varying said power supply voltage to said at least one portion;

said power supply voltage to said at least one portion is provided via one or more power gates configured to vary said power supply voltage to said at least one portion; and

said power supply is controlled to produce a finite non-zero error rate within said at least one portion.

8. A method of operating an integrated circuit, said method comprising the steps of:

detecting errors in operation of said integrated circuit;

repairing errors in operation of said integrated circuit; and

applying a power supply voltage to at least one portion of said integrated circuit using a power supply;

varying an error rate within said at least one portion by varying said power supply voltage applied to said at least one portion, wherein

said power supply voltage to said at least one portion is applied via one or more power gates configured to vary said power supply voltage to said at least one portion, and wherein said power supply is controlled to produce a finite non-zero error rate within said at least one portion.

9. The method of claim 8, wherein said at least one portion is a power domain within said integrated circuit.

10. The method of claim 8, comprising power supply control circuitry configured at least to control provision of said power supply via said one or more power gates.

11. The method of claim 9, wherein said integrated circuit comprises a plurality of power domains with respective power supplies, said power supplies varying to vary power consumption of said integrated circuit.

12. The method of claim 8, wherein said power supply is configured to apply a body bias voltage applied to said at least one portion.

13. The method of claim 8, wherein at least some of said one or more power gates are controlled so as to switch off said power supply voltage therethrough.