Memory controller and integrated circuit device for correcting errors in data read from memory cells

• US 9,448,881 B1
• Filed: 06/23/2015
• Issued: 09/20/2016
• Est. Priority Date: 01/29/2013
• Status: Active Grant

• Current Assignee: Microsemi Storage Solutions, Inc (Microchip Technology Incorporated)
• Original Assignee: Microsemi Storage Solutions, Inc (Microchip Technology Incorporated)
• Inventors: Marelli, Alessia, Micheloni, Rino, Onufryk, Peter Z., Norrie, Christopher I. W., Jaser, Ihab
• Primary Examiner(s): Abraham, Esaw
• Application Number:
  US14/747,952
• Time in Patent Office: 455 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/11 using multiple parity bits
• CPC Class Codes: H03M 13/1108 Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/116 Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/3715 Adaptation to the number of estimated errors or to the channel state
• CPC Class Codes: H03M 13/45 Soft decoding, i.e. using symbol reliability information H03M13/41 takes precedence

Abstract

An integrated circuit device for correcting errors in data read from memory cells includes a decoder, an encoder and a data management module. The data management module is configured to select a correctable raw bit error rate limit from a plurality of raw bit error rate limits by changing a code-rate used by the encoder, wherein a virtual change to the decoder and the encoder occur to change the code rate.

Claims

1. An integrated circuit device for correcting errors in data read from memory cells, comprising:

a decoder, the decoder is configured from a single parity check matrix associated with a low density parity check (LDPC) code;

an encoder, the encoder is configured from the parity check matrix; and

a data management module, the data management module is connected with the decoder and the encoder, the data management module is configured to select a correctable raw bit error rate limit from a plurality of raw bit error rate limits by changing a code-rate used by the encoder, wherein a virtual change to the decoder and the encoder occur to change the code rate.

2. The integrated circuit device of claim 1, wherein the LDPC code is a quasi cyclical parity check (QC-LDPC) code.

3. The integrated circuit device of claim 1, wherein the code-rate is changed by virtually bypassing a portion of the encoder and setting a log-likelihood ratio (LLR) for a number of bits in the encoder to a strong value.

4. The integrated circuit device of claim 1, wherein the code-rate is changed by virtually bypassing a portion of the decoder and setting a log-likelihood ratio (LLR) for a number of bits in the decoder to a strong value.

5. The integrated circuit device of claim 1, wherein the code-rate is changed when a number of bits corrected by the decoder crosses a threshold and the threshold is less than the correctable raw bit error rate limit of the code-rate in use during encoding.

6. The integrated circuit device of claim 1, wherein the code-rate is changed by virtually disabling a portion of the encoder and a portion of the decoder.

7. A memory controller comprising:

a decoder, the decoder configured from a single parity check matrix associated with a low density parity check (LDPC) code for correcting errors in data read from memory cells at a first time up to a first correctable raw bit error rate limit;

an encoder configured from the parity check matrix; and

a data management module, the data management module connected to the decoder and the encoder, the data management module configured to adjust the decoding at a subsequent time, the adjusting enabling the decoding to correct errors in data read from the memory cells up to a second correctable raw bit error rate limit;

wherein the decoder is configured to be switched from hard-decision decoding to soft-decision decoding and is configured to dynamically allocate a number of soft bits for soft-decision decoding on the fly which enables the decoder to correct errors occurring in data read from the memory cells at different correctable raw bit error rate limits.