Two-wire communication protocol engine

• US 9,448,959 B2
• Filed: 10/25/2013
• Issued: 09/20/2016
• Est. Priority Date: 10/05/2012
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Hooper, William, Kessler, Martin, Lahr, Lewis F., Giancioppo, Michael
• Primary Examiner(s): Myers, Paul R
• Application Number:
  US14/063,886
• Publication Number:
  US 20140101351A1
• Time in Patent Office: 1,061 Days
• Field of Search: 710/110
• US Class Current: 1/1
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4256 using a clocked protocol
• CPC Class Codes: G06F 13/4273 using a clocked protocol
• CPC Class Codes: H04B 3/50 Systems for transmission between fixed stations via two-conductor transmission lines H04B3/54 takes precedence
• CPC Class Codes: H04L 1/16 in which the return channel carries supervisory signals, e.g. repetition request signals
• CPC Class Codes: H04L 2001/0093 Point-to-multipoint

Abstract

In an example embodiment, a two-wire communication protocol engine manages control and data transmissions in a bi-directional, multi-node bus system where each node is connected over a twisted wire pair bus to another node. Some embodiments include a state machine that allows for synchronized updates of configuration data across the system, a distributed interrupt system, a synchronization pattern based on data coding used in the system, and data scrambling applied to a portion of the data transmitted over the twisted wire pair bus. The multi-node bus system comprises a master node and a plurality of slave nodes. The slave nodes can be powered over the twisted wire pair bus.

Claims

1. A master node circuit, comprising:

a two-wire communication protocol engine for a master node to manage control and data transmissions according to a two-wire communication protocol in a bi-directional, multi-node bus system, wherein the two-wire communication protocol engine allows for synchronized updates of configuration data across the multi-node bus system, wherein the multi-node bus system comprises a plurality of slave nodes, including a particular slave node, connected to the master node on the bus system using a two wire bus to connect each node to a next node;

wherein the configuration data specifies a number of downstream slots in which the slave node is to transmit its data, and a number of upstream slots in which the slave node is to transmit its data; and

wherein a counter of the two-wire communication protocol engine is to be set to a predetermined start value upon transmission, by the master node, of new configuration data to the slave node, the counter is to change in response to acknowledgments received from the slave nodes, and the two-wire communication protocol engine is to apply the new configuration data after the counter reaches a predetermined end value.

2. The master node circuit of claim 1, wherein the two-wire communication protocol includes a downstream portion and an upstream portion, wherein a control frame and downstream data are transmitted from the master node in the downstream portion, wherein a response frame and upstream data are transmitted to the master node in the upstream portion, and wherein each slave node is to use a synchronization pattern at a beginning of the control frame as a time base.

3. The master node circuit of claim 2, wherein the two-wire communication protocol uses clock-first transition on zero Differential Manchester coding, and wherein the synchronization pattern is encoded using a modification of the Differential Manchester coding.

4. The master node circuit of claim 3, wherein the two-wire communication protocol engine includes a decoder block, and wherein the decoder block is to detect the synchronization pattern using a clock recovered from the two-wire bus.

5. The master node circuit of claim 2, wherein the downstream portion and the upstream portion each comprises 1024 bits, wherein the control frame and the response frame each comprise 64 bits, and wherein a first 16 bits of each of the control frame and the response frame comprises the synchronization pattern.

6. The master node circuit of claim 2, wherein the two-wire communication protocol engine includes a scrambler that scrambles a portion of the data transmitted over the two-wire bus, and wherein the synchronization pattern and a frame count in the control frame and the response frame are not scrambled.

7. The master node circuit of claim 6, wherein the scrambler is to use a linear feedback shift register (LFSR) to generate a pseudo-random bit-stream to scramble the portion of the data.

8. The master node circuit of claim 1, wherein the two-wire communication protocol engine is to signal an interrupt to a host controller after receiving the interrupt from the particular slave node.

9. The master node circuit of claim 8, wherein the two-wire communication protocol engine is to perform a read of the particular slave node to acquire details on the interrupt, store the details locally to the master node, and clear the interrupt in the particular slave node.

10. The master node circuit of claim 1, wherein the two-wire communication protocol engine is to transmit a value of the counter to the plurality of slave nodes as the counter changes.

11. The master node circuit of claim 10, wherein the counter is a first counter, the predetermined start value is a first predetermined start value, the predetermined end value is a first predetermined end value, the slave node includes a second counter that is set to a second predetermined start value in response to receipt of the new configuration data, the second counter changes in response to receipt of the value of the first counter, and the slave node is to apply the new configuration data after the second counter reaches a second predetermined end value.

12. The master node circuit of claim 11, wherein the first predetermined start value is a same value as the second predetermined start value.

13. The master node circuit of claim 1, wherein the configuration data includes a number of downstream slots for the slave node to retransmit, and a number of upstream slots for the slave node to retransmit.

14. The master node circuit of claim 1, wherein the configuration data includes a number of downstream slots for the slave node to consume, and a number of upstream slots for the slave node to consume.

15. A method for facilitating communication between a master node and a plurality of slave nodes, comprising:

generating clock, synchronization and framing signals in a two-wire communication protocol for the plurality of slave nodes;

facilitating bi-directional transfer of data using a two-wire bus to connect each node to the next node;

synchronizing updates of configuration data across the plurality of slave nodes, wherein the configuration data includes a number of upstream data slots for a particular slave node to consume, and a number of downstream data slots for a particular slave node to consume; and

powering the slave nodes over the two wire bus;

wherein synchronizing updates of configuration data comprises setting a counter to a predetermined start value upon transmission of new configuration data to the plurality of slave nodes, changing the counter in response to acknowledgments received from the plurality of slave nodes, and applying the new configuration data after the counter reaches a predetermined end value.

16. The method of claim 15, further comprising:

transmitting a control frame and downstream data from the master node in a downstream portion of the two-wire communication protocol, wherein a synchronization pattern at a beginning of the control frame is used as a time base by each slave node; and

receiving a response frame and upstream data from the slave nodes in an upstream portion of the two-wire communication protocol.

17. A slave node circuit, comprising:

a two-wire communication protocol engine for a slave node to manage control and data transmissions according to a two-wire communication protocol in a bi-directional, multi-node bus system, wherein the two-wire communication protocol engine allows for synchronized updates of configuration data across the multi-node bus system, wherein the multi-node bus system comprises a master node and a plurality of slave nodes, including the slave node, interconnected on the bus system using a two-wire bus to connect each node to a next node;

wherein the configuration data specifies a number of downstream slots in which the slave node is to transmit its data, and a number of upstream slots in which the slave node is to transmit its data; and

wherein a counter of the two-wire communication protocol engine is to be set to a predetermined start value upon receipt, by the slave node from the master node, of new configuration data to the slave node, the counter is to change in response to updates from the master node, and the two-wire communication protocol engine is to apply the new configuration data after the counter reaches a predetermined end value.

18. The slave node circuit of claim 17, wherein the counter is a first counter, the predetermined start value is a first predetermined start value, the predetermined end value is a first predetermined end value, the master node includes a second counter that is set to a second predetermined start value in response to transmission of the new configuration data to the plurality of slave nodes, the second counter changes in response to receipt of acknowledgments from the plurality of slave nodes, and the master node is to apply the new configuration data after the second counter reaches a second predetermined end value.

19. The slave node circuit of claim 18, wherein the updates from the master node are values of the second counter.

20. The slave node circuit of claim 18, wherein the two-wire communication protocol engine is to apply the new configuration data upon concluding a first upstream transfer after the counter reaches a predetermined end value.