Prototype and emulation system for multiple custom prototype boards

• US 9,449,138 B2
• Filed: 08/05/2014
• Issued: 09/20/2016
• Est. Priority Date: 02/12/2010
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Chang, Yingtsai, Shei, Sweyyan, Chiu, Hung-Chun, Lin, Meng-Chyi, Mao, Hwa, Wang, Ming-Yang, Hsu, Yu-Chin
• Primary Examiner(s): LIN, SUN J
• Application Number:
  US14/452,368
• Publication Number:
  US 20140351777A1
• Time in Patent Office: 777 Days
• Field of Search: 716/106, 716/108, 716/111, 716/116, 716/136
• US Class Current: 1/1
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes a non-transitory computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. A compilation is performed in accordance with a description file.

Claims

1. A system for emulating a circuit design, the system comprising:

a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design, wherein the emulation interface is configured to provide timing and control information for at least the verify; and

a non-transitory computer readable storage medium comprising instructions, which when executed cause the host workstation to;

compile a portion of the circuit design and an associated verification module adapted to configure the FPGA, wherein a compilation is performed in accordance with a description file.

2. The system of claim 1, wherein the emulation interface is further configured to receive and process a plurality of probed signals.

3. The system of claim 2, wherein the emulation interface is further configured to receive and process a plurality of signal values associated with a subset of the plurality of probed signals.

4. The system of claim 3, wherein the emulation interface is further configured to store the plurality of signal values.

5. The system of claim 1, wherein the description file includes a description of a board including the FPGA.

6. The system of claim 1, wherein the emulation interface is further configured to communicate with the associated verification module.

7. The system of claim 1, wherein the verification module is configured to communicate with the portion of the circuit design in the FPGA using a plurality of probed signals.

8. The system of claim 1, wherein the emulation interface is further configured to run a plurality of emulation cycles.

9. The system of claim 8, wherein the compilation is configured such that the emulation cycles are controlled by a plurality of clocks generated by a software component running on the host workstation, when the host workstation is invoked to run the software component.

10. The system of claim 8, wherein the compilation is configured such that the emulation cycles are controlled by a plurality of clocks generated by a board including the FPGA.

11. The system of claim 10, wherein the compilation is further configured such that a subset of the plurality of clocks is suspended when a message from a software component running on the host workstation is received by the emulation interface.

12. The system of claim 1, wherein the emulation interface is further configured to transmit a plurality of input signals to the verification module.

13. The system of claim 12, wherein the compilation is configured such that a subset of the plurality of input signals control a state associated with the FPGA.

14. The system of claim 12, wherein the compilation is configured such that a plurality of probed signals are used to verify the portion of the circuit design in accordance with a subset of the plurality of input signals.

15. The system of claim 14, wherein the emulation interface is further configured such that a plurality of signal values associated with a subset of the plurality of probed signals is captured in accordance with a subset of the plurality of input signals.

16. The system of claim 1 further comprising:

a plurality of FPGAs each configured to emulate and verify a different one of a plurality of portions of the circuit design; and

a non-transitory computer readable storage medium comprising instructions, which when executed further cause the host workstation to;

compile one of the plurality of portions of the circuit design and an associated different one of a plurality of verification modules adapted to configure a different one of the plurality of FPGAs.

17. The system of claim 16, wherein each of the plurality of FPGAs is on a board.

18. The system of claim 16, wherein each of the plurality of FPGAs is on a different one of a plurality of boards.

19. The system of claim 18 further comprising a plurality of emulation interfaces coupled to the host workstation, wherein each of the plurality of emulation interfaces is coupled to a different one of the plurality of boards.

20. The system of claim 1 further comprising a target component controlled by the emulated circuit design, wherein the target component is not in the host workstation, emulation interface, or a board including the FPGA.

21. A method for emulating a circuit design, the method comprising:

emulating and verifying the circuit design using a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) when the host workstation is invoked to verify the circuit design;

providing timing and control information via the emulation interface for at least the verifying; and

compiling a portion of the circuit design and an associated verification module to configure the FPGA, wherein the compiling is performed in accordance with a description file.

22. The method of claim 21, wherein the emulation interface receives and processes a plurality of probed signals.

23. The method of claim 22, wherein the emulation interface receives and processes a plurality of signal values associated with a subset of the plurality of probed signals.

24. The method of claim 23, wherein the emulation interface stores the plurality of signal values.

25. The method of claim 21, wherein the description file includes a description of a board including the FPGA.

26. The method of claim 21, wherein the emulation interface communicates with the associated verification module.

27. The method of claim 21, wherein the verification module communicates with the portion of the circuit design in the FPGA using a plurality of probed signals.

28. The method of claim 21, wherein the emulation interface runs a plurality of emulation cycles.

29. The method of claim 28, wherein the emulation cycles are controlled by a plurality of clocks generated by a software component running on the host workstation, when the host workstation is invoked to run the software component.

30. The method of claim 28, wherein the emulation cycles are controlled by a plurality of clocks generated by a board including the FPGA.

31. The method of claim 30, wherein a subset of the plurality of clocks is suspended when a message from a software component running on the host workstation is received by the emulation interface.

32. The method of claim 21, wherein the emulation interface transmits a plurality of input signals to the verification module.

33. The method of claim 32, wherein a subset of the plurality of input signals control a state associated with the FPGA.

34. The method of claim 32, wherein a plurality of probed signals are used to verify the portion of the circuit design in accordance with a subset of the plurality of input signals.

35. The method of claim 34, wherein a plurality of signal values associated with a subset of the plurality of probed signals is captured by the emulation interface in accordance with a subset of the plurality of input signals.

36. The method of claim 21 further comprising:

emulating and verifying one of a plurality of portions of the circuit design using a different one of a plurality of FPGAs; and

compiling, using the host workstation, one of the plurality of portions of the circuit design and an associated different one of a plurality of verification modules to configure a different one of the plurality of FPGAs.

37. The method of claim 36, wherein each of the plurality of FPGAs is on a board.

38. The method of claim 36, wherein each of the plurality of FPGAs is on a different one of a plurality of boards.

39. The method of claim 38 further comprising coupling a plurality of emulation interfaces to the host workstation, wherein each of the plurality of emulation interfaces is coupled to a different one of the plurality of boards.

40. The method of claim 21 further comprising controlling a target component by the emulated circuit design, wherein the target component is not in the host workstation, emulation interface, or a board including the FPGA.