Low standby power with fast turn on for non-volatile memory devices

• US 9,449,655 B1
• Filed: 12/11/2015
• Issued: 09/20/2016
• Est. Priority Date: 08/31/2015
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Zonte, Cristinel, Argrawal, Vineet, Raghavan, Vijay, Gradinariu, Iulian C., Moscaluk, Gary Peter, Bettman, Roger, Leshner, Samuel
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US14/966,990
• Time in Patent Office: 284 Days
• Field of Search: 365/185.23, 365/230.06, 365/226, 365/227, 365/228, 365/229, 365/185.18, 365/185.21
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.

Claims

1. An apparatus comprising:

a non-volatile memory device comprising a plurality of drivers; and

a standby control circuit coupled to the non-volatile memory device, the standby control circuit comprising;

a standby detection circuit to detect a standby condition;

a wake-up detection circuit to detect a wake condition; and

a bias control circuit coupled to the plurality of drivers, the standby detection circuit, and the wake-up detection circuit, the bias control circuit to control bias currents supplied to the plurality of drivers based on at least one of the standby condition and the wake condition, wherein an output frequency of at least one of the plurality of drivers is adjustable responsive to a change in the bias current.

2. The apparatus of claim 1, wherein the bias control circuit comprises:

a first current mirror coupled to the standby detection circuit; and

a second current mirror coupled to the standby detection circuit,

wherein the second current mirror operates in response to receiving an output from the standby detection circuit indicating the non-volatile memory device is in an active mode.

3. The apparatus of claim 1, wherein the at least one of the plurality of drivers includes a frequency oscillator, wherein the standby control circuit further comprises a voltage doubler coupled to the frequency oscillator, the voltage doubler to increase current to the non-volatile memory device in response to increased frequency from the frequency oscillator.

4. The apparatus of claim 1, wherein the standby control circuit further comprises:

a first distributed analog driver coupled to a first sector the non-volatile memory device; and

a second distributed analog driver coupled to a second sector the non-volatile memory device,

wherein the first distributed analog driver and the second distributed analog driver are coupled to the bias control circuit.

5. The apparatus of claim 1 wherein the standby detection circuit provides an indication that the device is in a standby mode if there is no read request for at least three clock cycles of the non-volatile memory device.

6. The apparatus of claim 1 wherein the non-volatile memory device is a charge trapping memory device.

7. The apparatus of claim 1 wherein the non-volatile memory device is a silicon oxide nitride oxide silicon (SONOS) memory device.

8. A method comprising:

detecting a standby operating condition of a non-volatile memory device;

detecting that the non-volatile memory device is not in a wake-up mode; and

reducing bias currents provided to drivers of the non-volatile memory device in response to detecting the standby operating condition, wherein reducing the bias currents reduces a frequency of an output of at least one of the drivers.

9. The method of claim 8, wherein reducing the bias currents provided to driving circuits comprises:

reducing a first bias current provided to a frequency oscillator;

reducing a second bias current provided to distributed analog drivers; and

reducing a third bias current provided to voltage drivers of read path circuits of the non-volatile memory device.

10. The method of claim 8, further comprising:

detecting a read instruction that accesses data from the non-volatile memory device; and

increasing the bias currents provided to drivers of the non-volatile memory device in response to detecting the read instruction.

11. The method of claim 10, wherein increasing the bias currents provided to drivers of the non-volatile memory device comprises increasing the bias current to a frequency oscillator to increase the frequency of the output of the frequency oscillator, wherein increasing the frequency from the frequency oscillator increases the current provided to read path circuits of the non-volatile memory device.

12. The method of claim 10 wherein increasing the bias currents to driving circuits of the non-volatile memory device comprises increasing the current to an analog driver of the non-volatile memory device.

13. The method of claim 8 further comprising:

detecting an instruction to wake-up from a sleep state; and

increasing the bias currents to driving circuits of the non-volatile memory device in response to detecting the instruction to wake-up from the sleep state.

14. The method of claim 8 wherein the non-volatile memory device is a charge trapping memory device.

15. The method of claim 8 wherein the non-volatile memory device is a silicon oxide nitride oxide silicon (SONOS) memory device.

16. A system comprising:

a non-volatile memory device comprising a plurality of drivers; and

a standby control circuit coupled to the non-volatile memory device, the standby control circuit comprising;

a standby detection circuit to detect that the non-volatile memory device is in a standby condition; and

a bias control circuit coupled to the standby detection circuit to provide bias currents to the plurality of drivers of the non-volatile memory device in a standby mode in response to a determination that the non-volatile memory device is in a standby condition, wherein an output frequency of at least one of the plurality of drivers is adjustable responsive to a change in the bias current.

17. The system of claim 16, wherein the system further comprises a wake-up detection circuit to detect that the non-volatile memory device is in a wake-up mode wherein the bias control circuit provides bias currents to the plurality of drivers of the non-volatile memory device in an active mode in response to detecting that the non-volatile memory device is in a wake condition.

18. The system of claim 16, wherein the system further comprises:

a first distributed analog driver coupled to a first sector the non-volatile memory device; and

a second distributed analog driver coupled to a second sector the non-volatile memory device,

wherein the first distributed analog driver and the second distributed analog driver are coupled to the bias control circuit.

19. The system of claim 16 wherein the non-volatile memory device is a charge trapping memory device.

20. The system of claim 16 wherein the non-volatile memory device is a silicon oxide nitride oxide silicon (SONOS) memory device.