Dynamic redundancy repair

• US 9,449,720 B1
• Filed: 11/17/2015
• Issued: 09/20/2016
• Est. Priority Date: 11/17/2015
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lung, Hsiang-Lan
• Primary Examiner(s): Nguyen, Hien
• Application Number:
  US14/943,366
• Time in Patent Office: 308 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/781 combined in a redundant decoder

Abstract

The disclosed memory device technology for implementing dynamic device repair includes a memory array, a redundancy array and a redundancy mapping store. The memory array includes memory cells and the redundant array includes redundancy cells. The memory device also includes circuitry configured to execute a write operation and a read operation in response to respective commands, using a dynamic redundancy repair method to replace the temporary defective cells in the memory array with the redundancy cells in the redundancy array.

Claims

1. A memory device, comprising:

a memory array having a plurality of memory cells;

a redundancy array having a plurality of redundancy cells;

a redundancy mapping store having entries to map addresses of memory cells in the memory array to addresses of redundancy cells; and

circuitry coupled to the redundancy array and the memory array, which executes a write operation in response to a write command,

the write operation writing a data value having a selected address in the memory array whether or not there is a valid entry for the selected address in the redundancy mapping store, applying a write/verify cycle to a memory cell in the memory array having the selected address, and if the selected memory cell fails verify, then writing the data value to a redundancy cell in the redundancy array and changing or writing an entry to the redundancy mapping store to map the selected address to the redundancy cell.

2. The memory device of claim 1, including if the selected memory cell passes verify in the write operation, then removing or marking invalid an entry in the redundancy mapping store for the selected address.

3. The memory device of claim 1, in a subsequent write operation to the selected address in the memory array, applying a write/verify cycle to the memory cell in the memory array having the selected address, and if the selected memory cell passes verify, then removing or marking invalid the entry in the redundancy mapping store for the selected address.

4. The memory device of claim 2 wherein the redundancy cell mapped to the selected address can be used to store another data value for a different address.

5. The memory device of claim 1 further comprising a memory address decoder and a redundancy address decoder coupled to the memory array and the redundancy array, respectively.

6. The memory device of claim 1, wherein the redundancy mapping store is coupled to a memory address decoder and a redundancy address decoder.

7. The memory device of claim 1, wherein a second write operation includes writing a second data value having the selected address in the memory array, whether or not there is a valid entry for the selected address in the redundancy mapping store, applying a write/verify cycle to the memory cell in the memory array having the selected address, and if the selected memory cell fails verify, then writing the second data value to a redundancy cell which can be the same as or different than the redundancy cell stored the data value.

8. The memory device of claim 1 further comprising a second mapping store having entries to map addresses of hard fail bits in the memory array to addresses of redundancy cells in a second redundancy array.

9. The memory device of claim 8, wherein the redundancy cells in the redundancy array are available for substitution for soft fail bits in the memory array, and the redundancy cells in a second redundancy array are available for substitution for hard fail bits in the memory array.

10. The memory device of claim 8 further comprising a second redundancy address decoder coupled to the second redundancy array.

11. A method of writing a memory device including a memory array having a plurality of memory cells, a redundant array having a plurality of redundancy cells, and redundancy mapping store having entries to map addresses of memory cells in the memory array to addresses of redundancy cells, the method comprising:

writing a data value having a selected address in the memory array whether or not there is a valid entry for the selected address in the redundancy mapping store, applying a write/verify cycle to a memory cell in the memory array having the selected address, and if the selected memory cell fails verify, then writing the data value to a redundancy cell in the redundancy array and changing or writing an entry to the redundancy mapping store to map the selected address to the redundancy cell.

12. The method of claim 11 further comprising if the selected memory cell passes verify in the write operation, then removing or marking invalid an entry in the redundancy mapping store for the selected address.

13. The method of claim 11, in a subsequent write operation to the selected address in the memory array, applying a write/verify cycle to the memory cell in the memory array having the selected address, and if the selected memory cell passes verify, then removing or marking invalid the entry in the redundancy mapping store for the selected address.

14. The method of claim 11 wherein the redundancy cell mapped to the selected address can be used to store another data value for a different address.

15. The method of claim 11 further comprising disabling a memory decoder coupled to the memory array and enabling a redundancy decoder coupled to the redundancy array if there is a valid entry for the selected address in the redundancy mapping store.

16. The method of claim 11, wherein the memory device further comprises a second plurality of redundancy cells in a second redundancy array.

17. The method of claim 16, wherein the memory device further comprises a second redundancy address decoder coupled to the second redundancy array.

18. The method of claim 11, wherein the plurality of redundancy cells in the redundancy array are available for substitution for soft fail bits in the memory array.

19. The method of claim 16, wherein the second plurality of redundancy cells in the second redundancy array are available for substitution for hard fail bits in the memory array.

20. The method of claim 11 further comprising a second mapping store having entries to map addresses of hard fail bits in the memory array to addresses of redundancy cells in a second redundancy array.